Lines Matching +full:irqs +full:- +full:reserved
1 // SPDX-License-Identifier: GPL-2.0
3 * ip30-irq.c: Highlevel interrupt handling for IP30 architecture.
18 #include "ip30-common.h"
36 return -ENOSPC; in heart_alloc_int()
50 pending = heart_read(&heart_regs->isr); in ip30_error_irq()
51 mask = heart_read(&heart_regs->imr[cpu]); in ip30_error_irq()
52 cause = heart_read(&heart_regs->cause); in ip30_error_irq()
59 /* Prevent any of the error IRQs from firing again. */ in ip30_error_irq()
60 heart_write(mask & ~(pending), &heart_regs->imr[cpu]); in ip30_error_irq()
62 /* Ack all error IRQs. */ in ip30_error_irq()
63 heart_write(HEART_L4_INT_MASK, &heart_regs->clear_isr); in ip30_error_irq()
67 * through the error IRQs and report a "heart attack" for each one in ip30_error_irq()
80 err_reg = heart_read(&heart_regs->mem_err_addr); in ip30_error_irq()
84 /* i = 63; i >= 51; i-- */ in ip30_error_irq()
85 for (i = HEART_ERR_MASK_END; i >= HEART_ERR_MASK_START; i--) in ip30_error_irq()
93 /* Unmask the error IRQs. */ in ip30_error_irq()
94 heart_write(mask, &heart_regs->imr[cpu]); in ip30_error_irq()
104 pend = heart_read(&heart_regs->isr); in ip30_normal_irq()
105 mask = (heart_read(&heart_regs->imr[cpu]) & in ip30_normal_irq()
115 &heart_regs->clear_isr); in ip30_normal_irq()
119 &heart_regs->clear_isr); in ip30_normal_irq()
123 &heart_regs->clear_isr); in ip30_normal_irq()
127 &heart_regs->clear_isr); in ip30_normal_irq()
141 heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr); in ip30_ack_heart_irq()
147 unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu); in ip30_mask_heart_irq()
149 clear_bit(d->hwirq, mask); in ip30_mask_heart_irq()
150 heart_write(*mask, &heart_regs->imr[hd->cpu]); in ip30_mask_heart_irq()
156 unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu); in ip30_mask_and_ack_heart_irq()
158 clear_bit(d->hwirq, mask); in ip30_mask_and_ack_heart_irq()
159 heart_write(*mask, &heart_regs->imr[hd->cpu]); in ip30_mask_and_ack_heart_irq()
160 heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr); in ip30_mask_and_ack_heart_irq()
166 unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu); in ip30_unmask_heart_irq()
168 set_bit(d->hwirq, mask); in ip30_unmask_heart_irq()
169 heart_write(*mask, &heart_regs->imr[hd->cpu]); in ip30_unmask_heart_irq()
178 return -EINVAL; in ip30_set_heart_irq_affinity()
183 hd->cpu = cpumask_first_and(mask, cpu_online_mask); in ip30_set_heart_irq_affinity()
188 irq_data_update_effective_affinity(d, cpumask_of(hd->cpu)); in ip30_set_heart_irq_affinity()
210 return -EINVAL; in heart_domain_alloc()
214 return -ENOMEM; in heart_domain_alloc()
219 return -EAGAIN; in heart_domain_alloc()
237 clear_bit(irqd->hwirq, heart_irq_map); in heart_domain_free()
238 kfree(irqd->chip_data); in heart_domain_free()
254 &heart_regs->clear_isr); in ip30_install_ipi()
257 &heart_regs->clear_isr); in ip30_install_ipi()
259 heart_write(*mask, &heart_regs->imr[cpu]); in ip30_install_ipi()
271 /* Mask all IRQs. */ in arch_init_irq()
272 heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[0]); in arch_init_irq()
273 heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[1]); in arch_init_irq()
274 heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[2]); in arch_init_irq()
275 heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[3]); in arch_init_irq()
278 heart_write(HEART_ACK_ALL_MASK, &heart_regs->clear_isr); in arch_init_irq()
280 /* Enable specific HEART error IRQs for each CPU. */ in arch_init_irq()
283 heart_write(*mask, &heart_regs->imr[0]); in arch_init_irq()
286 heart_write(*mask, &heart_regs->imr[1]); in arch_init_irq()
289 * Some HEART bits are reserved by hardware or by software convention. in arch_init_irq()
290 * Mark these as reserved right away so they won't be accidentally in arch_init_irq()