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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dnuvoton,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim LIU <JJLIU0@nuvoton.com>
20 to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO.
22 - Support interrupt option for each input port and various interrupt
23 sensitivity options (level-high, level-low, edge-high, edge-low)
24 - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines.
25 nuvoton,input-ngpios GPIO lines is only for GPI.
26 nuvoton,output-ngpios GPIO lines is only for GPO.
[all …]
Daspeed,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
17 - Support interrupt option for each input port and various interrupt
18 sensitivity option (level-high, level-low, edge-high, edge-low)
19 - Support reset tolerance option for each output port
20 - Directly connected to APB bus and its shift clock is from APB bus clock
22 - Co-work with external signal-chained TTL components (74LV165/74LV595)
27 - aspeed,ast2400-sgpio
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Dgpio-ts4900.txt1 * Technologic Systems I2C-FPGA's GPIO controller bindings
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
5 uses 2 bits: it doesn't use a dedicated input bit.
8 - compatible: Should be one of the following
9 "technologic,ts4900-gpio"
10 "technologic,ts7970-gpio"
11 - reg: Physical base address of the controller and length
13 - #gpio-cells: Should be two. The first cell is the pin number.
14 - gpio-controller: Marks the device node as a gpio controller.
17 - ngpios: Number of GPIOs this controller is instantiated with,
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Dgpio-pisosr.txt1 Generic Parallel-in/Serial-out Shift Register GPIO Driver
3 This binding describes generic parallel-in/serial-out shift register
4 devices that can be used for GPI (General Purpose Input). This includes
5 SN74165 serial-out shift registers and the SN65HVS88x series of
9 - compatible : Should be "pisosr-gpio".
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two. For consumer use see gpio.txt.
14 - ngpios : Number of used GPIO lines (0..n-1), default is 8.
15 - load-gpios : GPIO pin specifier attached to load enable, this
17 load input pin values into the device.
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Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
48 include/dt-bindings/gpio/gpio.h whenever possible:
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/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
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Dintel,pinctrl-keembay.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
14 of pin directions, input/output values and configuration
19 const: intel,keembay-pinctrl
24 gpio-controller: true
26 '#gpio-cells':
29 ngpios:
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Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
15 controller. It controls the input/output settings on the available pins and
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
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/linux-6.12.1/drivers/gpio/
Dgpio-loongson-64bit.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2022-2023 Loongson Technology Corporation Limited
46 int input) in loongson_commit_direction() argument
48 u8 bval = input ? 1 : 0; in loongson_commit_direction()
50 writeb(bval, lgpio->reg_base + lgpio->chip_data->conf_offset + pin); in loongson_commit_direction()
57 writeb(bval, lgpio->reg_base + lgpio->chip_data->out_offset + pin); in loongson_commit_level()
65 spin_lock_irqsave(&lgpio->lock, flags); in loongson_gpio_direction_input()
67 spin_unlock_irqrestore(&lgpio->lock, flags); in loongson_gpio_direction_input()
77 spin_lock_irqsave(&lgpio->lock, flags); in loongson_gpio_direction_output()
80 spin_unlock_irqrestore(&lgpio->lock, flags); in loongson_gpio_direction_output()
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Dgpio-aspeed-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
49 * Note: The "value" register returns the input value when the GPIO is
50 * configured as an input.
110 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
112 return gpio->base + bank->rdata_reg; in bank_reg()
114 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
116 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
118 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
120 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
122 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
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Dgpio-em.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile GPIO Support - GIO
61 return ioread32(p->base0 + offs); in em_gio_read()
63 return ioread32(p->base1 + (offs - GIO_IDT0)); in em_gio_read()
70 iowrite32(value, p->base0 + offs); in em_gio_write()
72 iowrite32(value, p->base1 + (offs - GIO_IDT0)); in em_gio_write()
94 ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); in em_gio_irq_reqres()
96 dev_err(p->gpio_chip.parent, in em_gio_irq_reqres()
108 gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); in em_gio_irq_relres()
131 return -EINVAL; in em_gio_irq_set_type()
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Dgpio-npcm-sgpio.c1 // SPDX-License-Identifier: GPL-2.0
143 return gpio->base + bank->rdata_reg; in bank_reg()
145 return gpio->base + bank->wdata_reg; in bank_reg()
147 return gpio->base + bank->event_config; in bank_reg()
149 return gpio->base + bank->event_status; in bank_reg()
152 dev_WARN(gpio->chip.parent, "Getting here is an error condition"); in bank_reg()
175 *offset -= internal->nout_sgpio; in npcm_sgpio_irqd_to_data()
184 in_port = GPIO_BANK(gpio->nin_sgpio); in npcm_sgpio_init_port()
185 if (GPIO_BIT(gpio->nin_sgpio) > 0) in npcm_sgpio_init_port()
188 out_port = GPIO_BANK(gpio->nout_sgpio); in npcm_sgpio_init_port()
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Dgpio-realtek-otto.c1 // SPDX-License-Identifier: GPL-2.0-only
24 /* Clear bit (0) for input, set bit (1) for output */
42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data
49 * @bank_read: Read a bank setting as a single 32-bit value
50 * @bank_write: Write a bank setting as a single 32-bit value
53 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
54 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
55 * a value from (to) these registers. The IMR register consists of four 16-bit
56 * port values, packed into two 32-bit registers. Use @imr_line_pos to get the
57 * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than
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Dgpio-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/gpio/uniphier-gpio.h>
44 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. in uniphier_gpio_bank_to_reg()
65 spin_lock_irqsave(&priv->lock, flags); in uniphier_gpio_reg_update()
66 tmp = readl(priv->regs + reg); in uniphier_gpio_reg_update()
69 writel(tmp, priv->regs + reg); in uniphier_gpio_reg_update()
70 spin_unlock_irqrestore(&priv->lock, flags); in uniphier_gpio_reg_update()
107 return !!(readl(priv->regs + reg_offset) & mask); in uniphier_gpio_offset_read()
152 for_each_set_clump8(i, bank_mask, mask, chip->ngpio) { in uniphier_gpio_set_multiple()
166 return -ENXIO; in uniphier_gpio_to_irq()
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Dgpio-pisosr.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015-2023 Texas Instruments Incorporated - https://www.ti.com/
19 * struct pisosr_gpio - GPIO driver data
24 * @load_gpio: GPIO pin used to load input into device
40 mutex_lock(&gpio->lock); in pisosr_gpio_refresh()
42 if (gpio->load_gpio) { in pisosr_gpio_refresh()
43 gpiod_set_value_cansleep(gpio->load_gpio, 1); in pisosr_gpio_refresh()
45 gpiod_set_value_cansleep(gpio->load_gpio, 0); in pisosr_gpio_refresh()
49 ret = spi_read(gpio->spi, gpio->buffer, gpio->buffer_size); in pisosr_gpio_refresh()
51 mutex_unlock(&gpio->lock); in pisosr_gpio_refresh()
[all …]
/linux-6.12.1/include/linux/regulator/
Dgpio-regulator.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * gpio-regulator.h
14 * Roger Quadros <ext-roger.quadros@nokia.com>
27 * struct gpio_regulator_state - state description
29 * @gpios: bitfield of gpio target-states for the value
32 * and the necessary gpio-state to achieve it.
34 * The n-th bit in the bitfield describes the state of the n-th GPIO
35 * from the gpios-array defined in gpio_regulator_config below.
43 * struct gpio_regulator_config - config structure
45 * @input_supply: Name of the input regulator supply
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/linux-6.12.1/drivers/regulator/
Dgpio-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * gpio-regulator.c
14 * Roger Quadros <ext-roger.quadros@nokia.com>
17 * non-controllable regulators, as well as for allowing testing on
28 #include <linux/regulator/gpio-regulator.h>
50 for (ptr = 0; ptr < data->nr_states; ptr++) in gpio_regulator_get_value()
51 if (data->states[ptr].gpios == data->state) in gpio_regulator_get_value()
52 return data->states[ptr].value; in gpio_regulator_get_value()
54 return -EINVAL; in gpio_regulator_get_value()
64 for (ptr = 0; ptr < data->nr_states; ptr++) in gpio_regulator_set_voltage()
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/linux-6.12.1/arch/arm64/boot/dts/amd/
Delba.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include "dt-bindings/interrupt-controller/arm-gic.h"
11 compatible = "amd,pensando-elba";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 dma-coherent;
19 compatible = "fixed-clock";
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/linux-6.12.1/drivers/of/unittest-data/
Doverlay_gpio_01.dtso1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <0>;
10 compatible = "unittest-gpio";
12 gpio-controller;
13 #gpio-cells = <2>;
14 ngpios = <2>;
15 gpio-line-names = "line-A", "line-B";
17 line-b {
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Doverlay_gpio_03.dtso1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <0>;
10 compatible = "unittest-gpio";
12 gpio-controller;
13 #gpio-cells = <2>;
14 ngpios = <2>;
15 gpio-line-names = "line-A", "line-B", "line-C", "line-D";
17 line-d {
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/linux-6.12.1/Documentation/admin-guide/gpio/
Dgpio-sim.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
6 The configfs GPIO Simulator (gpio-sim) provides a way to create simulated GPIO
12 ------------------------
14 The gpio-sim module registers a configfs subsystem called ``'gpio-sim'``. For
21 **Group:** ``/config/gpio-sim``
23 This is the top directory of the gpio-sim configfs tree.
25 **Group:** ``/config/gpio-sim/gpio-device``
27 **Attribute:** ``/config/gpio-sim/gpio-device/dev_name``
29 **Attribute:** ``/config/gpio-sim/gpio-device/live``
32 attribute is read-only and allows the user-space to read the platform device
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/linux-6.12.1/drivers/pinctrl/
Dpinctrl-microchip-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
138 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
139 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
144 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
149 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr()
150 regmap_get_reg_stride(priv->regs); in sgpio_get_addr()
159 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl()
171 ret = regmap_write(priv->regs, addr, val); in sgpio_writel()
181 ret = regmap_update_bits(priv->regs, addr, clear | set, set); in sgpio_clrsetbits()
187 int width = priv->bitcount - 1; in sgpio_configure_bitstream()
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/linux-6.12.1/arch/arm/boot/dts/microchip/
Dlan966x-pcb8309.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x_pcb8309.dts - Device Tree file for PCB8309
5 /dts-v1/;
7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
10 model = "Microchip EVB - LAN9662";
11 compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966";
20 stdout-path = "serial0:115200n8";
23 gpio-restart {
24 compatible = "gpio-restart";
29 i2c-mux {
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/linux-6.12.1/drivers/pinctrl/tegra/
Dpinctrl-tegra.h1 /* SPDX-License-Identifier: GPL-2.0-only */
47 /* argument: Integer, range is HW-dependant */
49 /* argument: Integer, range is HW-dependant */
51 /* argument: Integer, range is HW-dependant */
53 /* argument: Integer, range is HW-dependant */
55 /* argument: Integer, range is HW-dependant */
75 * struct tegra_function - Tegra pinctrl mux function
87 * struct tegra_pingroup - Tegra pin group
97 * @pupd_reg: Pull-up/down register offset.
98 * @pupd_bank: Pull-up/down register bank.
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/linux-6.12.1/include/linux/gpio/
Ddriver.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pinctrl/pinconf-generic.h>
48 * struct gpio_irq_chip - GPIO interrupt controller
78 * If non-NULL, will be set as the parent of this GPIO interrupt
90 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
98 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
113 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
269 * is passed a bitmap in "valid_mask" and it will have ngpios
270 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
276 unsigned int ngpios);
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