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/linux-6.12.1/drivers/clk/rockchip/
Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
40 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
57 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
81 u32 delay; in rockchip_mmc_set_phase() local
97 return -EINVAL; in rockchip_mmc_set_phase()
104 * Due to the inexact nature of the "fine" delay, we might in rockchip_mmc_set_phase()
105 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
112 * On one extreme (if delay is actually 44ps): in rockchip_mmc_set_phase()
114 * The other (if delay is actually 77ps): in rockchip_mmc_set_phase()
[all …]
/linux-6.12.1/drivers/clk/mmp/
Dclk-apbc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/delay.h>
27 unsigned int delay; member
42 if (apbc->lock) in clk_apbc_prepare()
43 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
45 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
46 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
49 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
51 if (apbc->lock) in clk_apbc_prepare()
52 spin_unlock_irqrestore(apbc->lock, flags); in clk_apbc_prepare()
[all …]
Dclk-gate.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
31 if (gate->lock) in mmp_clk_gate_enable()
32 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
34 tmp = readl(gate->reg); in mmp_clk_gate_enable()
35 tmp &= ~gate->mask; in mmp_clk_gate_enable()
36 tmp |= gate->val_enable; in mmp_clk_gate_enable()
37 writel(tmp, gate->reg); in mmp_clk_gate_enable()
39 if (gate->lock) in mmp_clk_gate_enable()
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/linux-6.12.1/tools/testing/selftests/net/netfilter/
Dconntrack_sctp_collision.sh2 # SPDX-License-Identifier: GPL-2.0
6 # 14:35:47.655279 IP CLIENT_IP.PORT > SERVER_IP.PORT: sctp (1) [INIT] [init tag: 2017837359]
7 # 14:35:48.353250 IP SERVER_IP.PORT > CLIENT_IP.PORT: sctp (1) [INIT] [init tag: 1187206187]
8 # 14:35:48.353275 IP CLIENT_IP.PORT > SERVER_IP.PORT: sctp (1) [INIT ACK] [init tag: 2017837359]
11 # 14:35:48.855335 IP SERVER_IP.PORT > CLIENT_IP.PORT: sctp (1) [INIT ACK] [init tag: 164579970]
13 # TOPO: SERVER_NS (link0)<--->(link1) ROUTER_NS (link2)<--->(link3) CLIENT_NS
29 ip -n "$SERVER_NS" link add link0 type veth peer name link1 netns "$ROUTER_NS"
30 ip -n "$CLIENT_NS" link add link3 type veth peer name link2 netns "$ROUTER_NS"
32 ip -n "$SERVER_NS" link set link0 up
33 ip -n "$SERVER_NS" addr add $SERVER_IP/24 dev link0
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/panel/
Dsamsung,s6e8aa0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
22 reset-gpios: true
23 display-timings: true
25 vdd3-supply:
28 vci-supply:
31 power-on-delay:
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/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
73 /* Defined for adding a delay to the input RX_CLK for better timing.
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
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/linux-6.12.1/drivers/clk/sunxi/
Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
[all …]
/linux-6.12.1/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
/linux-6.12.1/drivers/clk/
Dclk-palmas.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2013-2014 Texas Instruments, Inc.
13 #include <linux/clk-provider.h>
30 int delay; member
57 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, in palmas_clks_prepare()
58 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
59 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
60 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
62 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", in palmas_clks_prepare()
63 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
[all …]
/linux-6.12.1/drivers/media/i2c/
Dbt819.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * bt819 - BT819A VideoStream Decoder (Rockwell Part)
12 * - moved over to linux>=2.4.x i2c protocol (9/9/2002)
21 #include <linux/delay.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-ctrls.h>
29 MODULE_DESCRIPTION("Brooktree-819 video decoder driver");
35 MODULE_PARM_DESC(debug, "Debug level (0-1)");
38 /* ----------------------------------------------------------------------- */
57 return &container_of(ctrl->handler, struct bt819, hdl)->sd; in to_sd()
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/linux-6.12.1/drivers/media/test-drivers/vidtv/
Dvidtv_tuner.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 * struct vidtv_tuner_config - Configuration used to init the tuner.
22 * @mock_power_up_delay_msec: Simulate a power-up delay.
23 * @mock_tune_delay_msec: Simulate a tune delay.
24 * @vidtv_valid_dvb_t_freqs: The valid DVB-T frequencies to simulate.
25 * @vidtv_valid_dvb_c_freqs: The valid DVB-C frequencies to simulate.
26 * @vidtv_valid_dvb_s_freqs: The valid DVB-S frequencies to simulate.
30 * The configuration used to init the tuner module, usually filled
/linux-6.12.1/lib/
Dtest_objpool.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/delay.h>
53 int delay; /* ms */ member
61 /* per-cpu worker */
73 int delay; member
90 atomic_long_add(size, &test->data.kmalloc.alloc); in ot_kzalloc()
98 atomic_long_add(size, &test->data.kmalloc.free); in ot_kfree()
106 pr_info("memory allocation summary for %s\n", test->name); in ot_mem_report()
108 alloc = atomic_long_read(&test->data.kmalloc.alloc); in ot_mem_report()
109 free = atomic_long_read(&test->data.kmalloc.free); in ot_mem_report()
[all …]
/linux-6.12.1/drivers/clk/actions/
Dowl-pll.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 // Author: David Liu <liuwei@actions-semi.com>
14 #include "owl-common.h"
32 u8 delay; member
51 .delay = _delay, \
63 .hw.init = CLK_HW_INIT(_name, \
78 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
93 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
99 #define mul_mask(m) ((1 << ((m)->width)) - 1)
/linux-6.12.1/drivers/mmc/host/
Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "sdhci-pltfm.h"
19 /* HRS - Host Register Set (specific to Cadence) */
39 /* SRS - Slot Register Set (SDHCI-compatible) */
57 * The tuned val register is 6 bit-wide, but not the whole of the range is
58 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
85 int (*init)(struct platform_device *pdev); member
90 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
91 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
92 { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
[all …]
Dsdhci-of-dwcmshc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/arm-smccc.h>
14 #include <linux/dma-mapping.h>
24 #include "sdhci-pltfm.h"
41 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
51 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
53 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
151 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */
153 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */
154 #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */
[all …]
Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
46 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_get_internal_phase()
78 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()
79 struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; in rockchip_mmc_get_phase()
81 if (priv->internal_phase) in rockchip_mmc_get_phase()
89 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_set_internal_phase()
93 u32 delay; in rockchip_mmc_set_internal_phase() local
[all …]
/linux-6.12.1/arch/arm/lib/
Ddelay.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Delay loops based on the OpenRISC implementation.
11 #include <linux/delay.h>
12 #include <linux/init.h>
18 * Default to the loop-based delay implementation.
21 .delay = __loop_delay,
33 return -ENXIO; in read_current_timer()
35 *timer_val = delay_timer->read_current_timer(); in read_current_timer()
49 while ((get_cycles() - start) < cycles) in __timer_delay()
70 clocks_calc_mult_shift(&new_mult, &new_shift, timer->freq, in register_current_timer_delay()
[all …]
/linux-6.12.1/drivers/hwmon/pmbus/
Dmax15301.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * extensive empirical testing has revealed that auto-detection of
9 * limit-registers will fail in a random fashion unless the delay
10 * parameter is set to above about 80us. The default delay is set
16 #include <linux/init.h>
21 #include <linux/delay.h>
41 static ushort delay = MAX15301_WAIT_TIME; variable
42 module_param(delay, ushort, 0644);
43 MODULE_PARM_DESC(delay, "Delay between chip accesses in us");
63 if (!i2c_check_functionality(client->adapter, in max15301_probe()
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Ddp.c32 #include <subdev/bios/init.h>
42 #define AMPERE_IED_HACK(disp) ((disp)->engine.subdev.device->card_type >= GA100)
53 *pid = BIT(outp->index); in nvkm_dp_mst_id_get()
60 int ret = nvkm_i2c_aux_acquire(outp->dp.aux); in nvkm_dp_aux_xfer()
65 ret = nvkm_i2c_aux_xfer(outp->dp.aux, false, type, addr, data, size); in nvkm_dp_aux_xfer()
66 nvkm_i2c_aux_release(outp->dp.aux); in nvkm_dp_aux_xfer()
73 outp->dp.enabled = pu; in nvkm_dp_aux_pwr()
74 nvkm_dp_enable(outp, outp->dp.enabled); in nvkm_dp_aux_pwr()
92 nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay) in nvkm_dp_train_sense() argument
94 struct nvkm_outp *outp = lt->outp; in nvkm_dp_train_sense()
[all …]
/linux-6.12.1/init/
Dcalibrate.c1 // SPDX-License-Identifier: GPL-2.0
2 /* calibrate.c: default delay calibration
4 * Excised from init/main.c
9 #include <linux/delay.h>
10 #include <linux/init.h>
28 * loops per jiffy directly, instead of guessing it using delay().
29 * Also, this code tries to handle non-maskable asynchronous events
44 int max = -1; /* index of measured_times with max/min values or not set */ in calibrate_delay_direct()
45 int min = -1; in calibrate_delay_direct()
60 * 1. pre_start <- When we are sure that jiffy switch hasn't happened in calibrate_delay_direct()
[all …]
/linux-6.12.1/drivers/spi/
Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
104 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
[all …]
/linux-6.12.1/arch/parisc/lib/
Ddelay.c1 // SPDX-License-Identifier: GPL-2.0
3 * Precise Delay Loops for parisc
17 #include <linux/init.h>
19 #include <asm/delay.h>
23 /* CR16 based delay: */
40 if ((now - bclock) >= loops) in __cr16_delay()
51 * since CR16's are per-cpu we need to calculate in __cr16_delay()
52 * that. The delay must guarantee that we wait "at in __cr16_delay()
59 loops -= (now - bclock); in __cr16_delay()
/linux-6.12.1/arch/x86/include/asm/
Di8259.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/delay.h>
33 /* the PIC may need a careful delay on some platforms, hence specific calls */
39 * delay for some accesses to PIC on motherboard or in chipset in inb_pic()
51 * delay for some accesses to PIC on motherboard or in chipset in outb_pic()
66 void (*init)(int auto_eoi); member
84 return legacy_pic->nr_legacy_irqs; in nr_legacy_irqs()
/linux-6.12.1/kernel/locking/
Dlocktorture.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Module-based torture test facility for locking
28 #include <linux/delay.h>
38 torture_param(int, call_rcu_chains, 0, "Self-propagate call_rcu() chains during test (0=disable).");
41 torture_param(int, nreaders_stress, -1, "Number of read-locking stress-test threads");
42 torture_param(int, nwriters_stress, -1, "Number of write-locking stress-test threads");
46 "Do periodic rt-boost. 0=Disable, 1=Only for rt_mutex, 2=For all lock types.");
47 torture_param(int, rt_boost_factor, 50, "A factor determining how often rt-boost happens.");
69 cpumask_var_t *cm_bind = kp->arg; in param_set_cpumask()
75 ret = -ENOMEM; in param_set_cpumask()
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/linux-6.12.1/Documentation/fb/
Ddeferred_io.rst5 Deferred IO is a way to delay and repurpose IO. It uses host memory as a
10 - userspace app like Xfbdev mmaps framebuffer
11 - deferred IO and driver sets up fault and page_mkwrite handlers
12 - userspace app tries to write to mmapped vaddress
13 - we get pagefault and reach fault handler
14 - fault handler finds and returns physical page
15 - we get page_mkwrite where we add this page to a list
16 - schedule a workqueue task to be run after a delay
17 - app continues writing to that page with no additional cost. this is
19 - the workqueue task comes in and mkcleans the pages on the list, then
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