mmc/host/sdhci-cadence.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "sdhci-pltfm.h"
19 /* HRS - Host Register Set (specific to Cadence) */
39 /* SRS - Slot Register Set (SDHCI-compatible) */
57  * The tuned val register is 6 bit-wide, but not the whole of the range is
58  * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
85 	int (*init)(struct platform_device *pdev);  member
90 	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
91 	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
92 	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
93 	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
94 	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
95 	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
96 	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
97 	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
98 	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
99 	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
100 	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
112 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;  in sdhci_cdns_write_phy_reg()
123 	priv->priv_writel(priv, tmp, reg);  in sdhci_cdns_write_phy_reg()
126 	priv->priv_writel(priv, tmp, reg);  in sdhci_cdns_write_phy_reg()
133 	priv->priv_writel(priv, tmp, reg);  in sdhci_cdns_write_phy_reg()
156 	struct sdhci_cdns_phy_param *p = priv->phy_params;  in sdhci_cdns_phy_param_parse()
166 		p->addr = sdhci_cdns_phy_cfgs[i].addr;  in sdhci_cdns_phy_param_parse()
167 		p->data = val;  in sdhci_cdns_phy_param_parse()
176 	for (i = 0; i < priv->nr_phy_params; i++) {  in sdhci_cdns_phy_init()
177 		ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,  in sdhci_cdns_phy_init()
178 					       priv->phy_params[i].data);  in sdhci_cdns_phy_init()
199 	return host->max_clk;  in sdhci_cdns_get_timeout_clock()
207 	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);  in sdhci_cdns_set_emmc_mode()
210 	priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);  in sdhci_cdns_set_emmc_mode()
217 	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);  in sdhci_cdns_get_emmc_mode()
224 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;  in sdhci_cdns_set_tune_val()
229 		return -EINVAL;  in sdhci_cdns_set_tune_val()
242 		priv->priv_writel(priv, tmp, reg);  in sdhci_cdns_set_tune_val()
267 	 * The delay is set by probe, based on the DT properties.  in sdhci_cdns_execute_tuning()
269 	if (host->timing != MMC_TIMING_MMC_HS200 &&  in sdhci_cdns_execute_tuning()
270 	    host->timing != MMC_TIMING_UHS_SDR104)  in sdhci_cdns_execute_tuning()
275 		    mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */  in sdhci_cdns_execute_tuning()
287 		dev_err(mmc_dev(host->mmc), "no tuning point found\n");  in sdhci_cdns_execute_tuning()
288 		return -EIO;  in sdhci_cdns_execute_tuning()
291 	return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);  in sdhci_cdns_execute_tuning()
311 		if (priv->enhanced_strobe)  in sdhci_cdns_set_uhs_signaling()
328 /* Elba control register bits [6:3] are byte-lane enables */
332  * The Pensando Elba SoC explicitly controls byte-lane enabling on writes
334  * is used to ensure byte-lane enable, using write control (ctl_addr),
342 	spin_lock_irqsave(&priv->wrlock, flags);  in elba_priv_writel()
343 	writel(GENMASK(7, 3), priv->ctl_addr);  in elba_priv_writel()
345 	spin_unlock_irqrestore(&priv->wrlock, flags);  in elba_priv_writel()
350 	elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg);  in elba_write_l()
361 	spin_lock_irqsave(&priv->wrlock, flags);  in elba_write_w()
362 	writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);  in elba_write_w()
363 	writew(val, host->ioaddr + reg);  in elba_write_w()
364 	spin_unlock_irqrestore(&priv->wrlock, flags);  in elba_write_w()
375 	spin_lock_irqsave(&priv->wrlock, flags);  in elba_write_b()
376 	writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);  in elba_write_b()
377 	writeb(val, host->ioaddr + reg);  in elba_write_b()
378 	spin_unlock_irqrestore(&priv->wrlock, flags);  in elba_write_b()
398 	host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA;  in elba_drv_init()
399 	spin_lock_init(&priv->wrlock);  in elba_drv_init()
401 	/* Byte-lane control register */  in elba_drv_init()
406 	priv->ctl_addr = ioaddr;  in elba_drv_init()
407 	priv->priv_writel = elba_priv_writel;  in elba_drv_init()
408 	writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);  in elba_drv_init()
430 	.init = elba_drv_init,
449 	priv->enhanced_strobe = ios->enhanced_strobe;  in sdhci_cdns_hs400_enhanced_strobe()
453 	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)  in sdhci_cdns_hs400_enhanced_strobe()
457 	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)  in sdhci_cdns_hs400_enhanced_strobe()
467 	dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n");  in sdhci_cdns_mmc_hw_reset()
469 	reset_control_assert(priv->rst_hw);  in sdhci_cdns_mmc_hw_reset()
473 	reset_control_deassert(priv->rst_hw);  in sdhci_cdns_mmc_hw_reset()
487 	struct device *dev = &pdev->dev;  in sdhci_cdns_probe()
498 	nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);  in sdhci_cdns_probe()
499 	host = sdhci_pltfm_init(pdev, &data->pltfm_data,  in sdhci_cdns_probe()
505 	pltfm_host->clk = clk;  in sdhci_cdns_probe()
508 	priv->nr_phy_params = nr_phy_params;  in sdhci_cdns_probe()
509 	priv->hrs_addr = host->ioaddr;  in sdhci_cdns_probe()
510 	priv->enhanced_strobe = false;  in sdhci_cdns_probe()
511 	priv->priv_writel = cdns_writel;  in sdhci_cdns_probe()
512 	host->ioaddr += SDHCI_CDNS_SRS_BASE;  in sdhci_cdns_probe()
513 	host->mmc_host_ops.hs400_enhanced_strobe =  in sdhci_cdns_probe()
515 	if (data->init) {  in sdhci_cdns_probe()
516 		ret = data->init(pdev);  in sdhci_cdns_probe()
525 	ret = mmc_of_parse(host->mmc);  in sdhci_cdns_probe()
529 	sdhci_cdns_phy_param_parse(dev->of_node, priv);  in sdhci_cdns_probe()
535 	if (host->mmc->caps & MMC_CAP_HW_RESET) {  in sdhci_cdns_probe()
536 		priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL);  in sdhci_cdns_probe()
537 		if (IS_ERR(priv->rst_hw)) {  in sdhci_cdns_probe()
538 			ret = dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw),  in sdhci_cdns_probe()
542 		if (priv->rst_hw)  in sdhci_cdns_probe()
543 			host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset;  in sdhci_cdns_probe()
564 	ret = clk_prepare_enable(pltfm_host->clk);  in sdhci_cdns_resume()
579 	clk_disable_unprepare(pltfm_host->clk);  in sdhci_cdns_resume()
591 		.compatible = "socionext,uniphier-sd4hc",
595 		.compatible = "amd,pensando-elba-sd4hc",
605 		.name = "sdhci-cdns",