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/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Datmel,sama5d4-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/atmel,sama5d4-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - atmel,sama5d4-wdt
20 - microchip,sam9x60-wdt
21 - microchip,sama7g5-wdt
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Datmel,at91sam9-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/watchdog/atmel,at91sam9-wdt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Eugen Hristev <eugen.hristev@microchip.com>
15 const: atmel,at91sam9260-wdt
26 atmel,max-heartbeat-sec:
32 atmel,min-heartbeat-sec:
35 must be smaller than the max-heartbeat-sec value. It is used to
39 atmel,watchdog-type:
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/linux-6.12.1/drivers/cpuidle/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "CPU Idle"
5 bool "CPU idle PM support"
10 CPU idle is a generic framework for supporting software-controlled
11 idle processor power management. It includes modular cross-platform
14 If you're using an ACPI-enabled platform, you should say Y here.
30 This governor implements a simplified idle state selection method
40 This governor implements haltpoll idle state selection, to be
42 for polling for a certain amount of time before entering idle
54 menu "ARM CPU Idle Drivers"
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Dcpuidle-clps711x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * CLPS711X CPU idle driver
14 #define CLPS711X_CPUIDLE_NAME "clps711x-cpuidle"
30 .name = "HALT",
31 .desc = "CLPS711X HALT",
/linux-6.12.1/Documentation/virt/kvm/
Dhalt-polling.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The KVM halt polling system
7 The KVM halt polling system provides a feature within KVM whereby the latency
16 the order of a few micro-seconds, although performance benefits are workload
19 invoked. Thus halt polling is especially useful on workloads with very short
20 wakeup periods where the time spent halt polling is minimised and the time
23 The generic halt polling code is implemented in:
27 The powerpc kvm-hv specific case is implemented in:
31 Halt Polling Interval
35 as the halt polling interval, is increased and decreased based on the perceived
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/linux-6.12.1/arch/x86/kernel/
Dprocess.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/sched/idle.h>
21 #include <linux/user-return-notifier.h>
27 #include <linux/elf-randomize.h>
31 #include <linux/entry-common.h>
47 #include <asm/spec-ctrl.h>
59 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
60 * no more per-task TSS's. The TSS size is kept cacheline-aligned
62 * section. Since TSS's are completely CPU-local, we want them
63 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
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/linux-6.12.1/drivers/cpuidle/governors/
Dhaltpoll.c1 // SPDX-License-Identifier: GPL-2.0
3 * haltpoll.c - haltpoll idle governor
8 * the COPYING file in the top-level directory.
31 /* multiplication factor to grow per-cpu poll_limit_ns */
35 /* value in us to start growing per-cpu halt_poll_ns */
39 /* allow shrinking guest halt poll */
44 * haltpoll_select - selects the next idle state to enter
53 s64 latency_req = cpuidle_governor_latency_req(dev->cpu); in haltpoll_select()
55 if (!drv->state_count || latency_req == 0) { in haltpoll_select()
60 if (dev->poll_limit_ns == 0) in haltpoll_select()
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/linux-6.12.1/arch/alpha/kernel/
Dhead.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 * switched into OSF/1 PAL-code, and loaded us at the correct address
8 * the kernel global pointer and jump to the kernel entry-point.
12 #include <asm/asm-offsets.h>
29 lda $30,0x4000 - SIZEOF_PT_REGS($8)
39 /* On entry here from SRM console, the HWPCB of the per-cpu
42 of the target idle task. */
88 # It is handy, on occasion, to make halt actually just loop.
94 .globl halt symbol
95 .ent halt
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/linux-6.12.1/arch/arc/kernel/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -- Added support for Inter Processor Interrupts
9 * -- Initial Write (Borrowed heavily from ARM)
49 return -EINVAL; in arc_get_cpu_map()
52 return -EINVAL; in arc_get_cpu_map()
59 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
65 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
66 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
81 * - Initialise the CPU possible map early - this describes the CPUs
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/linux-6.12.1/drivers/watchdog/
Dat91sam9_wdt.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * Watchdog Timer (WDT) - System peripherals regsters.
36 #define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */
37 #define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */
/linux-6.12.1/Documentation/virt/
Dguest-halt-polling.rst2 Guest halt polling
15 2) The VM-exit cost can be avoided.
25 ("per-cpu guest_halt_poll_ns"), which is adjusted by the algorithm
42 Division factor used to shrink per-cpu guest_halt_poll_ns when
49 Multiplication factor used to grow per-cpu guest_halt_poll_ns
50 when event occurs after per-cpu guest_halt_poll_ns
57 The per-cpu guest_halt_poll_ns eventually reaches zero
58 in case of an idle system. This value sets the initial
59 per-cpu guest_halt_poll_ns when growing. This can
70 to avoid it (per-cpu guest_halt_poll_ns will remain
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/linux-6.12.1/Documentation/networking/device_drivers/ethernet/toshiba/
Dspider_net.rst1 .. SPDX-License-Identifier: GPL-2.0
29 "full" and "not-in-use". An "empty" or "ready" descriptor is ready
31 and is waiting to be emptied and processed by the OS. A "not-in-use"
40 buffers, processing them, and re-marking them empty.
50 interrupt, and halt processing.
54 descr. The OS will process this descr, and then mark it "not-in-use",
57 all of those behind it should be "not-in-use". When RX traffic is not
59 The OS will then note that the current tail is "empty", and halt
62 The head pointer (somewhat mis-named) follows after the tail pointer.
64 a "not-in-use" descr. The OS will perform various housekeeping duties
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/linux-6.12.1/arch/mips/include/asm/octeon/
Dcvmx-dpi-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
184 uint64_t idle:1; member
190 uint64_t idle:1;
201 uint64_t idle:1; member
209 uint64_t idle:1;
777 uint64_t halt:1; member
801 uint64_t halt:1;
808 uint64_t halt:1; member
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/linux-6.12.1/drivers/acpi/
Dacpi_pad.c1 // SPDX-License-Identifier: GPL-2.0-only
66 (highest_subcstate - 1); in power_saving_mwait_init()
83 /* TSC could halt in idle */ in power_saving_mwait_init()
90 static int tsk_in_cpu[NR_CPUS] = {[0 ... NR_CPUS-1] = -1};
97 unsigned long min_weight = -1; in round_robin_cpu()
123 if (tsk_in_cpu[tsk_index] != -1) in round_robin_cpu()
139 if (tsk_in_cpu[tsk_index] != -1) { in exit_round_robin()
141 tsk_in_cpu[tsk_index] = -1; in exit_round_robin()
167 expire_time = jiffies + HZ * (100 - idle_pct) / 100; in power_saving_thread()
171 /* TSC could halt in idle, so notify users */ in power_saving_thread()
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/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsc7280-chrome-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
20 /delete-node/ &cdsp_mem;
21 /delete-node/ &domain_idle_states;
22 /delete-node/ &gpu_zap_mem;
23 /delete-node/ &gpu_zap_shader;
24 /delete-node/ &hyp_mem;
25 /delete-node/ &xbl_mem;
26 /delete-node/ &reserved_xbl_uefi_log;
27 /delete-node/ &sec_apps_mem;
31 domain_idle_states: domain-idle-states {
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/linux-6.12.1/arch/mips/kernel/
Dsmp-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/mips-cps.h>
22 #include <asm/pm-cps.h>
26 #include <asm/smp-cps.h>
101 0x0, CSEGX_SIZE - 1); in allocate_cps_vecs()
109 0x0, SZ_4G - 1); in allocate_cps_vecs()
116 return -ENOMEM; in allocate_cps_vecs()
167 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { in cps_smp_setup()
207 /* If we have an FPU, enroll ourselves in the FPU-full mask */ in cps_smp_setup()
221 pr_err("core_entry address unsuitable, disabling smp-cps\n"); in cps_prepare_cpus()
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Dpm-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <asm/asm-offsets.h>
16 #include <asm/idle.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
22 #include <asm/smp-cps.h>
26 * cps_nc_entry_fn - type of a generated non-coherent state entry function
28 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
30 * The code entering & exiting non-coherent states is generated at runtime
33 * core-specific code particularly for cache routines. If coupled_coherence
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/linux-6.12.1/arch/x86/include/asm/
Dirqflags.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/processor-flags.h>
9 #include <asm/nospec-branch.h>
15 /* Declaration required for gcc < 4.9 to prevent -Werror=missing-prototypes */
23 * it evaluates its effective address -- this is part of the in native_save_fl()
101 * Used in the idle loop; sti takes one instruction cycle
113 static __always_inline void halt(void) in halt() function
/linux-6.12.1/Documentation/arch/x86/
Dmds.rst7 --------
12 - Microarchitectural Store Buffer Data Sampling (MSBDS) (CVE-2018-12126)
13 - Microarchitectural Fill Buffer Data Sampling (MFBDS) (CVE-2018-12130)
14 - Microarchitectural Load Port Data Sampling (MLPDS) (CVE-2018-12127)
15 - Microarchitectural Data Sampling Uncacheable Memory (MDSUM) (CVE-2019-11091)
18 dependent load (store-to-load forwarding) as an optimization. The forward
21 buffers are partitioned between Hyper-Threads so cross thread forwarding is
32 Hyper-Threads so cross thread leakage is possible.
39 exploited eventually. Load ports are shared between Hyper-Threads so cross
48 --------------------
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/linux-6.12.1/arch/openrisc/kernel/
Dprocess.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
13 * This file handles the architecture-dependent parts of process handling...
50 * Used at user space -> kernel transitions.
63 /* Whoops - the platform was unable to reboot. Tell the user! */ in machine_restart()
64 pr_emerg("Reboot failed -- System halted\n"); in machine_restart()
69 * This is used if a sys-off handler was not set by a power management
80 * here to freeze the system for e.g. post-mortem debug purpose when
81 * possible. This halt has nothing to do with the idle halt.
85 printk(KERN_INFO "*** MACHINE HALT ***\n"); in machine_halt()
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/linux-6.12.1/drivers/net/fddi/skfp/h/
Dsupern_2.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
48 #define FS_SSRCRTG (1<<12) /* if SA has set MSB (source-routing)*/
54 #define FS_SFRMTY2 (1<<6) /* frame-class bit */
55 #define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */
56 #define FS_SFRMTY0 (1<<4) /* frame-type bit (LLC) */
58 #define FS_ERFBB0 (1<<0) /* - " - */
95 unsigned int rx_sadrrg :1 ; /* DA == MA or broad-/multicast */
97 unsigned int rx_seac0 :1 ; /* frame-copied C-indicator */
98 unsigned int rx_seac1 :1 ; /* address-match A-indicator */
99 unsigned int rx_seac2 :1 ; /* frame-error E-indicator */
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/linux-6.12.1/Documentation/admin-guide/pm/
Dintel_idle.rst1 .. SPDX-License-Identifier: GPL-2.0
5 ``intel_idle`` CPU Idle Time Management Driver
17 :doc:`CPU idle time management subsystem <cpuidle>` in the Linux kernel
18 (``CPUIdle``). It is the default CPU idle time management driver for the
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
27 logical CPU executing it is idle and so it may be possible to put some of the
28 processor's functional blocks into low-power states. That instruction takes two
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
44 Enumeration of Idle States
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Dcpuidle.rst1 .. SPDX-License-Identifier: GPL-2.0
8 CPU Idle Time Management
21 memory or executed. Those states are the *idle* states of the processor.
23 Since part of the processor hardware is not used in idle states, entering them
27 CPU idle time management is an energy-efficiency feature concerned about using
28 the idle states of processors for this purpose.
31 ------------
33 CPU idle time management operates on CPUs as seen by the *CPU scheduler* (that
37 software as individual single-core processors. In other words, a CPU is an
44 enter an idle state, that applies to the processor as a whole.
[all …]
/linux-6.12.1/arch/arm/mach-tegra/
Dsleep.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
12 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
14 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
16 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
18 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
20 #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
25 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
50 /* returns the offset of the flow controller halt register for a cpu */
74 /* loads a 32-bit value into a register without a data access */
/linux-6.12.1/drivers/cpufreq/
Dlonghaul.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2001-2004 Dave Jones.
13 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
16 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
146 /* Change frequency on next halt or sleep */ in do_longhaul1()
150 halt(); in do_longhaul1()
187 halt(); in do_powersaver()
192 /* Dummy op - must do something useless after P_LVL3 in do_powersaver()
200 /* Change frequency on next halt or sleep */ in do_powersaver()
205 halt(); in do_powersaver()
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