Searched +full:hip06 +full:- +full:lpc (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Hisilicon HiP06 Low Pin Count device10 - Wei Xu <xuwei5@hisilicon.com>13 Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which15 HiP06 is based on arm64 architecture where there is no I/O space. So, the17 LPC device node.21 pattern: '^isa@[0-9a-f]+$'[all …]
1 // SPDX-License-Identifier: GPL-2.0+22 #define DRV_NAME "hisi-lpc"50 #define LPC_REG_OP_LEN 0x10 /* LPC cycles count per start */58 /* The minimal nanosecond interval for each query on LPC cycle status */66 * for extra 256 lpc clocks, so (256 + 13) * 30ns = 8 us. The maximum burst84 return (status & LPC_REG_OP_STATUS_FINISHED) ? 0 : -EIO; in wait_lpc_idle()86 } while (--waitcnt); in wait_lpc_idle()88 return -ETIMEDOUT; in wait_lpc_idle()92 * hisi_lpc_target_in - trigger a series of LPC cycles for read operation93 * @lpcdev: pointer to hisi lpc device[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 #include <dt-bindings/interrupt-controller/arm-gic.h>11 compatible = "hisilicon,hip06-d03";12 interrupt-parent = <&gic>;13 #address-cells = <2>;14 #size-cells = <2>;17 compatible = "arm,psci-0.2";22 #address-cells = <1>;23 #size-cells = <0>;25 cpu-map {[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 #include <dt-bindings/interrupt-controller/arm-gic.h>11 compatible = "hisilicon,hip07-d05";12 interrupt-parent = <&gic>;13 #address-cells = <2>;14 #size-cells = <2>;17 compatible = "arm,psci-0.2";22 #address-cells = <1>;23 #size-cells = <0>;25 cpu-map {[all …]