arm/hisilicon/low-pin-count.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon HiP06 Low Pin Count device
10   - Wei Xu <xuwei5@hisilicon.com>
13   Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
15   HiP06 is based on arm64 architecture where there is no I/O space. So, the
17   LPC device node.
21     pattern: '^isa@[0-9a-f]+$'
28       - hisilicon,hip06-lpc
29       - hisilicon,hip07-lpc
34   '#address-cells':
37   '#size-cells':
41   - compatible
42   - reg
48   - |
50         compatible = "hisilicon,hip06-lpc";
51         #address-cells = <2>;
52         #size-cells = <1>;
56             compatible = "ipmi-bt";