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/linux-6.12.1/Documentation/devicetree/bindings/reset/
Dhisilicon,hi3660-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon System Reset Controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 Please also refer to reset.txt in this directory for common reset
15 The reset controller registers are part of the system-ctl block on
16 hi3660 and hi3670 SoCs.
21 - items:
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/linux-6.12.1/drivers/clk/hisilicon/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 bool "Hi3660 Clock Driver"
31 Build the clock driver for hi3660.
56 bool "HiSilicon Reset Controller Driver"
60 Build reset controller driver for HiSilicon device chipsets.
71 bool "Hi3660 Stub Clock Driver" if EXPERT
76 Build the Hisilicon Hi3660 stub clock driver.
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o
8 obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
9 obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
10 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
11 obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
12 obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
13 obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o
14 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
15 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
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/linux-6.12.1/drivers/reset/hisilicon/
Dreset-hi3660.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2016-2017 Linaro Ltd.
4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
12 #include <linux/reset-controller.h>
30 return regmap_write(rc->map, offset, mask); in hi3660_reset_program_hw()
32 return regmap_write(rc->map, offset + 4, mask); in hi3660_reset_program_hw()
60 .reset = hi3660_reset_dev,
70 offset = reset_spec->args[0]; in hi3660_reset_xlate()
71 bit = reset_spec->args[1]; in hi3660_reset_xlate()
79 struct device_node *np = pdev->dev.of_node; in hi3660_reset_probe()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Hi3660 Reset Driver"
7 Build the Hisilicon Hi3660 reset driver.
10 tristate "Hi6220 Reset Driver"
14 Build the Hisilicon Hi6220 reset driver.
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
3 obj-$(CONFIG_COMMON_RESET_HI3660) += reset-hi3660.o
/linux-6.12.1/arch/arm64/boot/dts/hisilicon/
Dhi3660.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Hisilicon Hi3660 SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "hisilicon,hi3660";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
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Dhi3670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
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Dhi3660-hikey960.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "hi3660.dtsi"
12 #include "hikey960-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/usb/pd.h>
20 compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
35 stdout-path = "serial6:115200n8";
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/linux-6.12.1/Documentation/devicetree/bindings/ufs/
Dhisilicon,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Wei <liwei213@huawei.com>
18 - hisilicon,hi3660-ufs
19 - hisilicon,hi3670-ufs
21 - compatible
24 - $ref: ufs-common.yaml
29 - items:
30 - const: hisilicon,hi3660-ufs
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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dhisilicon,kirin-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xiaowei Song <songxiaowei@hisilicon.com>
11 - Binghui Wang <wangbinghui@hisilicon.com>
17 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - hisilicon,kirin960-pcie
27 - hisilicon,kirin970-pcie
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/linux-6.12.1/drivers/ufs/host/
Dufs-hisi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2016-2017 Linaro Ltd.
6 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
14 #include <linux/dma-mapping.h>
16 #include <linux/reset.h>
19 #include "ufshcd-pltfrm.h"
21 #include "ufs-hisi.h"
57 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_hisi_check_hibern8()
61 err = -1; in ufs_hisi_check_hibern8()
62 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", in ufs_hisi_check_hibern8()
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/linux-6.12.1/drivers/pci/controller/dwc/
Dpcie-kirin.c1 // SPDX-License-Identifier: GPL-2.0
27 #include "pcie-designware.h"
29 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
58 * in-board Ethernet adapter and the other two connected to M.2 and mini
81 /* Per-slot PERST# */
86 /* Per-slot clkreq */
140 writel(val, hi3660_pcie_phy->base + reg); in kirin_apb_phy_writel()
146 return readl(hi3660_pcie_phy->base + reg); in kirin_apb_phy_readl()
151 struct device *dev = phy->dev; in hi3660_pcie_phy_get_clk()
153 phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref"); in hi3660_pcie_phy_get_clk()
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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