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/linux-6.12.1/tools/testing/selftests/drivers/net/netdevsim/
Dnexthop.sh2 # SPDX-License-Identifier: GPL-2.0
58 local nharg="$1"; shift
59 local expected="$1"; shift
61 out=$($IP nexthop show ${nharg} | sed -e 's/ *$//')
71 local group_id=$1; shift
78 nhid=$1; shift
79 expected=$1; shift
82 grep "trap" | wc -l)
93 local expected_occ=$1; shift
95 occ=$($DEVLINK -jp resource show $DEVLINK_DEV \
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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
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/linux-6.12.1/drivers/pinctrl/mediatek/
Dpinctrl-mtmips.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/pinctrl/pinconf-generic.h>
19 #include <asm/mach-ralink/ralink_regs.h>
20 #include <asm/mach-ralink/mt7620.h>
22 #include "pinctrl-mtmips.h"
24 #include "../pinctrl-utils.h"
50 return p->group_count; in mtmips_get_group_count()
54 unsigned int group) in mtmips_get_group_name() argument
58 return (group >= p->group_count) ? NULL : p->group_names[group]; in mtmips_get_group_name()
62 unsigned int group, in mtmips_get_group_pins() argument
[all …]
/linux-6.12.1/drivers/accessibility/speakup/
Di18n.c1 // SPDX-License-Identifier: GPL-2.0
57 [MSG_CTRL] = "control-",
73 [MSG_CTL_SHIFT] = "shift",
77 [MSG_CTL_LSHIFT] = "l shift",
81 [MSG_CTL_CAPSSHIFT] = "caps shift",
107 [MSG_STATE_SHIFT] = "shift",
151 [MSG_KEYNAME_LEFTSHFT] = "left shift",
163 [MSG_KEYNAME_RIGHTSHFT] = "right shift",
402 char *spk_msg_get(enum msg_index_t index) in spk_msg_get() argument
404 return speakup_msgs[index]; in spk_msg_get()
[all …]
/linux-6.12.1/drivers/pinctrl/samsung/
Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
116 .eint_mask = (1 << (pins)) - 1, \
140 .eint_mask = (1 << (pins)) - 1, \
194 .eint_mask = (1 << (pins)) - 1, \
200 * struct s3c64xx_eint0_data - EINT0 common data
212 * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
222 * struct s3c64xx_eint_gpio_data - GPIO EINT data
[all …]
/linux-6.12.1/net/mac80211/
Drc80211_minstrel_ht.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2013 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2019-2022 Intel Corporation
44 * Define group sort order: HT40 -> SGI -> #streams
50 _streams - 1
55 _MAX(0, 16 - __builtin_clz(duration))
57 /* MCS rate information for an MCS group */
61 .shift = _s, \
90 (_streams) - 1)
98 .shift = _s, \
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Drc80211_minstrel_ht.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 * a1 = exp(-pi * sqrt(2) / period)
29 * coeff3 = -sqr(a1)
30 * coeff1 = 1 - coeff2 - coeff3
32 #define MINSTREL_AVG_COEFF1 (MINSTREL_FRAC(1, 1) - \
33 MINSTREL_AVG_COEFF2 - \
36 #define MINSTREL_AVG_COEFF3 -0x0000092e
89 * - write static index to debugfs:ieee80211/phyX/rc/fixed_rate_idx
90 * - write -1 to enable RC processing again
91 * - setting will be applied on next update
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/linux-6.12.1/net/sched/
Dsch_qfq.c1 // SPDX-License-Identifier: GPL-2.0-only
26 "Reducing the Execution Time of Fair-Queueing Schedulers."
27 http://algo.ing.unimo.it/people/paolo/agg-sched/agg-sched.pdf
48 number of groups. Which group a class belongs to depends on the
59 QFQ_MAX_INDEX is the maximum index allowed for a group. We need
60 one bit per index.
67 ^.__grp->index = 0
68 *.__grp->slot_shift
72 The max group index corresponds to Lmax/w_min, where
75 we can derive the shift corresponding to each group.
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/linux-6.12.1/drivers/platform/mellanox/
Dmlxreg-io.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/hwmon-sysfs.h>
23 * struct mlxreg_io_priv_data - driver's private data:
30 * @group: sysfs attribute group;
31 * @groups: list of sysfs attribute group for hwmon registration;
41 struct attribute_group group; member
53 ret = regmap_read(regmap, data->reg, regval); in mlxreg_io_get_reg()
62 * with all bits one. No special handling for such kind of attributes - in mlxreg_io_get_reg()
65 * (from 1 to 32) is the bit sequence. For the fourth kind - the number in mlxreg_io_get_reg()
67 * specified through 'data->regnum' field. in mlxreg_io_get_reg()
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/linux-6.12.1/drivers/irqchip/
Dirq-riscv-aplic-msi.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-aplic.h>
13 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-aplic-main.h"
43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()
44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()
52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()
60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()
73 * Updating sourcecfg register for level-triggered interrupts in aplic_msi_irq_set_type()
84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg()
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Dirq-riscv-imsic-state.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear()
102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update()
106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update()
133 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync()
135 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
138 vec = &lpriv->vectors[i]; in __imsic_local_sync()
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/linux-6.12.1/arch/powerpc/include/asm/nohash/32/
Dmmu-8xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * During software tablewalk, the registers used perform mask/shift-add
21 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
43 * 4-15 => Not Used
62 #define MI_APG 0x000001e0 /* Access protection group (0) */
93 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
126 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
136 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
137 #define MD_APG 0x000001e0 /* Access protection group (0) */
175 #define MODULES_VADDR (MODULES_END - MODULES_SIZE)
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/linux-6.12.1/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.c6 * Maxime Ripard <maxime.ripard@free-electrons.com>
28 #include <linux/pinctrl/pinconf-generic.h>
33 #include <dt-bindings/pinctrl/sun4i-a10.h>
36 #include "pinctrl-sunxi.h"
51 * - Mux config
52 * - Data value
53 * - Drive level
54 * - Pull direction
62 u32 pin, u32 *reg, u32 *shift, u32 *mask) in sunxi_mux_reg() argument
67 *reg = bank * pctl->bank_mem_size + MUX_REGS_OFFSET + in sunxi_mux_reg()
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/linux-6.12.1/drivers/pinctrl/renesas/
Dpinctrl-rzv2m.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/pinconf-generic.h>
28 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
34 #define DRV_NAME "pinctrl-rzv2m"
60 * n indicates number of pins in the port, a is the register index
137 static void rzv2m_writel_we(void __iomem *addr, u8 shift, u8 value) in rzv2m_writel_we() argument
139 writel((BIT(16) | value) << shift, addr); in rzv2m_writel_we()
148 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
149 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
152 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; in rzv2m_pinctrl_set_pfc_mode()
[all …]
/linux-6.12.1/tools/testing/selftests/kvm/lib/aarch64/
Dgic_v3.c1 // SPDX-License-Identifier: GPL-2.0
48 GUEST_ASSERT(count--); in gicv3_gicd_wait_for_rwp()
64 GUEST_ASSERT(count--); in gicv3_gicr_wait_for_rwp()
124 * All other fields are read-only, so no need to read CTLR first. In in gicv3_set_eoi_split()
174 uint32_t fields_per_reg, index, mask, shift; in gicv3_access_reg() local
186 index = intid % fields_per_reg; in gicv3_access_reg()
187 shift = index * bits_per_field; in gicv3_access_reg()
188 mask = ((1U << bits_per_field) - 1) << shift; in gicv3_access_reg()
196 gicv3_setl_fields(cpu_or_dist, offset, mask, *val << shift); in gicv3_access_reg()
197 *val = gicv3_getl_fields(cpu_or_dist, offset, mask) >> shift; in gicv3_access_reg()
[all …]
/linux-6.12.1/arch/powerpc/mm/book3s64/
Dhash_64k.c31 * index from 0 - 15
33 bool __rpte_sub_valid(real_pte_t rpte, unsigned long index) in __rpte_sub_valid() argument
35 return !(hpte_soft_invalid(__rpte_to_hidx(rpte, index))); in __rpte_sub_valid()
48 unsigned long shift = mmu_psize_defs[MMU_PAGE_4K].shift; in __hash_page_4K() local
89 subpg_index = (ea & (PAGE_SIZE - 1)) >> shift; in __hash_page_4K()
118 gslot = pte_get_hash_gslot(vpn, shift, ssize, rpte, in __hash_page_4K()
128 if (ret == -1) in __hash_page_4K()
155 pa += (subpg_index << shift); in __hash_page_4K()
157 hash = hpt_hash(vpn, shift, ssize); in __hash_page_4K()
167 if (unlikely(slot == -1)) { in __hash_page_4K()
[all …]
Dhash_native.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 #include <asm/ppc-opcode.h>
28 #include <asm/feature-fixups.h>
30 #include <misc/cxl-base.h>
95 va &= ~((1ul << (64 - 52)) - 1); in ___tlbie()
106 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); in ___tlbie()
142 * re-order the tlbie in fixup_tlbie_vpn()
185 va &= ~((1ul << (64 - 52)) - 1); in __tlbiel()
196 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); in __tlbiel()
244 unsigned long *word = (unsigned long *)&hptep->v; in native_lock_hpte()
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/linux-6.12.1/drivers/pinctrl/freescale/
Dpinctrl-imx.c1 // SPDX-License-Identifier: GPL-2.0+
30 #include "pinctrl-imx.h"
43 for (i = 0; i < pctldev->num_groups; i++) { in imx_pinctrl_find_group_by_name()
45 if (grp && !strcmp(grp->grp.name, name)) in imx_pinctrl_find_group_by_name()
55 seq_printf(s, "%s", dev_name(pctldev->dev)); in imx_pin_dbg_show()
63 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_dt_node_to_map()
72 * first find the group of this node and check if we need create in imx_dt_node_to_map()
75 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); in imx_dt_node_to_map()
77 dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np); in imx_dt_node_to_map()
78 return -EINVAL; in imx_dt_node_to_map()
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/linux-6.12.1/drivers/scsi/cxlflash/
Dvlun.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 /* RHT - Resource Handle Table */
16 #define MC_CHUNK_SHIFT MC_RHT_NMASK /* shift to go from LBA to chunk# */
18 #define HIBIT (BITS_PER_LONG - 1)
23 * LXT - LBA Translation Table
25 * +-------+-------+-------+-------+-------+-------+-------+---+---+
27 * +-------+-------+-------+-------+-------+-------+-------+---+---+
32 * The LXT Entry also contains an index to a LUN TBL and a bitmask of which
33 * outgoing (FC) * ports can be selected. The port select bit-mask is ANDed
34 * with a global port select bit-mask maintained by the driver.
[all …]
/linux-6.12.1/drivers/soc/mediatek/
Dmtk-devapc.c1 // SPDX-License-Identifier: GPL-2.0
47 /* numbers of violation index */
64 reg = ctx->infra_base + ctx->data->regs_ofs->vio_sta_offset; in clear_vio_status()
66 for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) in clear_vio_status()
69 writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0), in clear_vio_status()
79 reg = ctx->infra_base + ctx->data->regs_ofs->vio_mask_offset; in mask_module_irq()
86 for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) in mask_module_irq()
91 val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, in mask_module_irq()
94 val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, in mask_module_irq()
103 * devapc_sync_vio_dbg - do "shift" mechansim" to get full violation information.
[all …]
/linux-6.12.1/drivers/comedi/drivers/
Ds626.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
68 * struct s626_private - Working data for s626 driver.
69 * @ai_cmd_running: non-zero if ai_cmd is running.
97 /* Counter overflow/index event flag masks for RDMISC2. */
98 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
110 writel(val, dev->mmio + reg); in s626_mc_enable()
116 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
124 val = readl(dev->mmio + reg); in s626_mc_test()
[all …]
/linux-6.12.1/arch/powerpc/platforms/powernv/
Dpci-ioda-tce.c1 // SPDX-License-Identifier: GPL-2.0+
22 struct pci_controller *hose = phb->hose; in pnv_ioda_parse_tce_sizes()
23 struct device_node *dn = hose->dn; in pnv_ioda_parse_tce_sizes()
28 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes"); in pnv_ioda_parse_tce_sizes()
39 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes", in pnv_ioda_parse_tce_sizes()
52 tbl->it_blocksize = 16; in pnv_pci_setup_iommu_table()
53 tbl->it_base = (unsigned long)tce_mem; in pnv_pci_setup_iommu_table()
54 tbl->it_page_shift = page_shift; in pnv_pci_setup_iommu_table()
55 tbl->it_offset = dma_offset >> tbl->it_page_shift; in pnv_pci_setup_iommu_table()
56 tbl->it_index = 0; in pnv_pci_setup_iommu_table()
[all …]
/linux-6.12.1/drivers/pinctrl/tegra/
Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
72 unsigned int shift; member
99 writel(value, padctl->regs + offset); in padctl_writel()
105 return readl(padctl->regs + offset); in padctl_readl()
112 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
116 unsigned int group) in tegra_xusb_padctl_get_group_name() argument
120 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name()
124 unsigned group, in tegra_xusb_padctl_get_group_pins() argument
[all …]
/linux-6.12.1/drivers/net/ethernet/freescale/
Ducc_geth.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
12 * - Rearrange code and style fixes
40 u8 res0[0x100 - sizeof(struct ucc_fast)];
45 u32 hafdup; /* half-duplex reg. */
56 u8 res3[0x180 - 0x15A];
85 successfully with the group address bit set
97 successfully with the group address bit set
104 u8 res5[0x200 - 0x1c4];
118 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues <<
[all …]
/linux-6.12.1/tools/testing/selftests/net/forwarding/
Drouter_mpath_seed.sh2 # SPDX-License-Identifier: GPL-2.0
4 # +-------------------------+ +-------------------------+
9 # +-------------------|-----+ +-|-----------------------+
11 # +-------------------|-----+ +-|-----------------------+
20 # +-------------------|-----+ +-|-----------------------+
22 # `----------'
39 ip -4 route add 192.0.2.32/28 vrf v$h1 nexthop via 192.0.2.2
40 ip -6 route add 2001:db8:3::/64 vrf v$h1 nexthop via 2001:db8:1::2
45 ip -6 route del 2001:db8:3::/64 vrf v$h1 nexthop via 2001:db8:1::2
46 ip -4 route del 192.0.2.32/28 vrf v$h1 nexthop via 192.0.2.2
[all …]

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