Lines Matching +full:group +full:- +full:index +full:- +full:shift

1 /* SPDX-License-Identifier: GPL-2.0 */
10  * During software tablewalk, the registers used perform mask/shift-add
21 #define MI_IDXMASK	0x00001f00	/* TLB index to be loaded */
43  * 4-15 => Not Used
62 #define MI_APG		0x000001e0	/* Access protection group (0) */
93 #define MD_IDXMASK	0x00001f00	/* TLB index to be loaded */
126 #define M_L1INDX	0x00000ffc	/* Level 1 index, when read */
136 #define MD_L2INDX	0xfffffe00	/* Level 2 index (*pte), when read */
137 #define MD_APG		0x000001e0	/* Access protection group (0) */
175 #define MODULES_VADDR	(MODULES_END - MODULES_SIZE)
196  *    shift : is the "PAGE_SHIFT" value for that page size
200 	unsigned int	shift;	/* number of bits */  member
205 static inline int shift_to_mmu_psize(unsigned int shift)  in shift_to_mmu_psize()  argument
210 		if (mmu_psize_defs[psize].shift == shift)  in shift_to_mmu_psize()
212 	return -1;  in shift_to_mmu_psize()
217 	if (mmu_psize_defs[mmu_psize].shift)  in mmu_psize_to_shift()
218 		return mmu_psize_defs[mmu_psize].shift;  in mmu_psize_to_shift()
225 	if (end - addr < size)  in arch_vmap_try_size()