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/linux-6.12.1/Documentation/devicetree/bindings/board/
Dfsl,fpga-qixis-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale on-board FPGA connected on I2C bus
10 - Frank Li <Frank.Li@nxp.com>
15 - items:
16 - enum:
17 - fsl,bsc9132qds-fpga
18 - const: fsl,fpga-qixis-i2c
[all …]
Dfsl,fpga-qixis.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale on-board FPGA/CPLD
10 - Frank Li <Frank.Li@nxp.com>
15 - items:
16 - const: fsl,p1022ds-fpga
17 - const: fsl,fpga-ngpixis
18 - items:
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/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Db4420qds.dts35 /include/ "b4420si-pre.dtsi"
43 board-control@3,0 {
44 compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
50 /include/ "b4420si-post.dtsi"
Dbsc9132qds.dtsi2 * BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,ifc-nand";
56 #address-cells = <1>;
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Db4860qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4860si-pre.dtsi"
50 board-control@3,0 {
51 compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
58 phy-handle = <&phy_sgmii_1e>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_1f>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&phy_xaui_slot1>;
69 phy-connection-type = "xgmii";
[all …]
Db4qds.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor, Inc.
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "cfi-flash";
61 bank-width = <2>;
62 device-width = <1>;
66 #address-cells = <1>;
[all …]
Dt1024qds.dts35 /include/ "t102xsi-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
44 reserved-memory {
45 #address-cells = <2>;
46 #size-cells = <2>;
49 bman_fbpr: bman-fbpr {
54 qman_fqd: qman-fqd {
59 qman_pfdr: qman-pfdr {
[all …]
Dt208xqds.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
42 reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
47 bman_fbpr: bman-fbpr {
51 qman_fqd: qman-fqd {
55 qman_pfdr: qman-pfdr {
[all …]
Dt104xqds.dtsi4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
37 #address-cells = <2>;
38 #size-cells = <2>;
39 interrupt-parent = <&mpic>;
68 reserved-memory {
69 #address-cells = <2>;
70 #size-cells = <2>;
73 bman_fbpr: bman-fbpr {
77 qman_fqd: qman-fqd {
81 qman_pfdr: qman-pfdr {
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Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
Dfsl-ls208xa-rdb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Copyright 2017-2020 NXP
18 #address-cells = <2>;
19 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "cfi-flash";
29 bank-width = <2>;
30 device-width = <1>;
34 compatible = "fsl,ifc-nand";
[all …]
Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
[all …]
Dfsl-ls1046a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2018-2019 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
20 emi1-slot1 = &ls1046mdio_s1;
21 emi1-slot2 = &ls1046mdio_s2;
22 emi1-slot4 = &ls1046mdio_s4;
27 qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
[all …]
Dfsl-ls1043a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
[all …]
Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
[all …]
Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
Dfsl-lx2162a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "LTM4619-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
/linux-6.12.1/arch/powerpc/platforms/85xx/
Dcorenet_generic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2009-2011 Freescale Semiconductor Inc.
19 #include <asm/pci-bridge.h>
20 #include <asm/ppc-pci.h>
62 .compatible = "simple-bus"
65 .compatible = "mdio-mux-gpio"
68 .compatible = "fsl,fpga-ngpixis"
71 .compatible = "fsl,fpga-qixis"
77 .compatible = "fsl,p4080-pcie",
80 .compatible = "fsl,qoriq-pcie-v2.2",
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