Lines Matching +full:fpga +full:- +full:qixis
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Copyright 2017-2020 NXP
18 #address-cells = <2>;
19 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "cfi-flash";
29 bank-width = <2>;
30 device-width = <1>;
34 compatible = "fsl,ifc-nand";
40 compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
47 i2c-mux@75 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 idle-state = <0>;
55 #address-cells = <1>;
56 #size-cells = <0>;
61 /* IRQ_RTC_B -> IRQ06, active low */
62 interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
67 #address-cells = <1>;
68 #size-cells = <0>;
74 shunt-resistor = <500>;
79 #address-cells = <1>;
80 #size-cells = <0>;
106 #address-cells = <1>;
107 #size-cells = <1>;
109 spi-max-frequency = <3000000>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "jedec,spi-nor";
121 spi-max-frequency = <50000000>;