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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dfixed-mmio-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple memory mapped IO fixed-rate clock sources
10 This binding describes a fixed-rate clock for which the frequency can
11 be read from a single 32-bit memory mapped I/O register.
17 - Jan Kotas <jank@cadence.com>
21 const: fixed-mmio-clock
26 "#clock-cells":
[all …]
/linux-6.12.1/drivers/phy/hisilicon/
Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
21 #include <dt-bindings/phy/phy.h>
37 int fixed; member
45 void __iomem *mmio; member
56 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
76 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
81 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode()
82 struct regmap *syscon = priv->syscon; in histb_combphy_set_mode()
88 switch (mode->select) { in histb_combphy_set_mode()
[all …]
/linux-6.12.1/drivers/clk/
Dclk-fixed-mmio.c1 // SPDX-License-Identifier: GPL-2.0
4 * Memory Mapped IO Fixed clock driver
12 #include <linux/clk-provider.h>
21 const char *clk_name = node->name; in fixed_mmio_clk_setup()
29 return ERR_PTR(-EIO); in fixed_mmio_clk_setup()
34 of_property_read_string(node, "clock-output-names", &clk_name); in fixed_mmio_clk_setup()
38 pr_err("%pOFn: failed to register fixed rate clock\n", node); in fixed_mmio_clk_setup()
44 pr_err("%pOFn: failed to add clock provider\n", node); in fixed_mmio_clk_setup()
56 CLK_OF_DECLARE(fixed_mmio_clk, "fixed-mmio-clock", of_fixed_mmio_clk_setup);
65 clk = fixed_mmio_clk_setup(pdev->dev.of_node); in of_fixed_mmio_clk_probe()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 # common clock types
3 obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
5 obj-$(CONFIG_CLK_KUNIT_TEST) += clk-test.o
6 clk-test-y := clk_test.o \
8 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
9 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
10 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
11 obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) += clk-fixed-rate-test.o
[all …]
/linux-6.12.1/arch/arc/boot/dts/
Dhaps_hs.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
5 /dts-v1/;
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&core_intc>;
24 … "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
[all …]
Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
[all …]
Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
33 /* 1 GHz fixed main PLL */
35 compatible = "fixed-clock";
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/arm/calxeda/
Dhb-sregs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Calxeda Highbank system has a block of MMIO registers controlling
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-sregs
28 - compatible
29 - reg
34 - |
[all …]
/linux-6.12.1/arch/arm/boot/dts/sigmastar/
Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
[all …]
/linux-6.12.1/arch/arm/boot/dts/nspire/
Dnspire.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&intc>;
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
27 compatible = "mmio-sram";
29 #address-cells = <1>;
30 #size-cells = <1>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 v2m_clk24mhz: clock-24000000 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "v2m:clk24mhz";
18 v2m_refclk1mhz: clock-1000000 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <1000000>;
[all …]
Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 stdout-path = "serial0:115200n8";
33 #address-cells = <2>;
[all …]
/linux-6.12.1/drivers/interconnect/qcom/
Dicc-rpm.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/interconnect-provider.h>
16 #include "icc-common.h"
17 #include "icc-rpm.h"
55 struct icc_provider *provider = src->provider; in qcom_icc_set_qnoc_qos()
57 struct qcom_icc_node *qn = src->data; in qcom_icc_set_qnoc_qos()
58 struct qcom_icc_qos *qos = &qn->qos; in qcom_icc_set_qnoc_qos()
61 rc = regmap_update_bits(qp->regmap, in qcom_icc_set_qnoc_qos()
62 qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port), in qcom_icc_set_qnoc_qos()
64 qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT); in qcom_icc_set_qnoc_qos()
[all …]
/linux-6.12.1/sound/soc/sh/
Dssi.c1 // SPDX-License-Identifier: GPL-2.0
24 * fixed TDM slot size, regardless of sample resolution.
54 #define CR_BREN (1 << 7) /* clock gating in burst mode */
62 #define SSIREG(reg) (*(unsigned long *)(ssi->mmio + (reg)))
65 unsigned long mmio; member
71 .mmio = 0xFE680000,
74 .mmio = 0xFE690000,
78 .mmio = 0xFFE70000,
86 * track usage of the SSI; it is simplex-only so prevent attempts of
92 struct ssi_priv *ssi = &ssi_cpu_data[dai->id]; in ssi_startup()
[all …]
/linux-6.12.1/drivers/ata/
Dsata_sx4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sata_sx4.c - Promise SATA
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2004 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
19 -------------------
29 PATA<->SATA bridges exist on SX4 boards, external to the
34 submitted and waited-on as a single unit), and an optional
39 transactions into a fixed DIMM memory space, from where an ATA
60 This is a very slow, lock-step way of doing things that can
[all …]
/linux-6.12.1/drivers/clocksource/
Dtimer-armada-370-xp.c1 // SPDX-License-Identifier: GPL-2.0
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * Timer 0 is used as free-running clocksource, while timer 1 is
14 * ---
19 * * Armada 370 has no 25 MHz fixed timer.
21 * * Armada XP cannot work properly without such 25 MHz fixed timer as
25 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
68 /* Global timers are connected to the coherency fabric clock, and the
74 * SoC-specific data.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/imx/
Dfsl-imx-drm.txt8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,imx-display-subsystem";
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
25 - imx51
26 - imx53
27 - imx6q
28 - imx6qp
29 - reg: should be register base and length as documented in the
[all …]
/linux-6.12.1/drivers/ssb/
Ddriver_pcicore.c3 * Broadcom PCI-core driver
28 return ssb_read32(pc->dev, offset); in pcicore_read32()
34 ssb_write32(pc->dev, offset, value); in pcicore_write32()
40 return ssb_read16(pc->dev, offset); in pcicore_read16()
46 ssb_write16(pc->dev, offset, value); in pcicore_write16()
62 /* Assume one-hot slot wiring */
79 if (pc->cardbusmode && (dev > 1)) in get_cfgspace_addr()
115 int err = -EINVAL; in ssb_extpci_read_config()
117 void __iomem *mmio; in ssb_extpci_read_config() local
119 WARN_ON(!pc->hostmode); in ssb_extpci_read_config()
[all …]
/linux-6.12.1/drivers/comedi/drivers/
Ds626.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
68 * struct s626_private - Working data for s626 driver.
69 * @ai_cmd_running: non-zero if ai_cmd is running.
98 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
110 writel(val, dev->mmio + reg); in s626_mc_enable()
116 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
124 val = readl(dev->mmio + reg); in s626_mc_test()
129 #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4)
[all …]
/linux-6.12.1/arch/arm64/boot/dts/intel/
Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
[all …]
/linux-6.12.1/drivers/gpu/drm/renesas/rcar-du/
Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
13 #include <linux/media-bus-format.h>
54 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
72 void __iomem *mmio; member
74 struct clk *mod; /* CPG module clock */
75 struct clk *extal; /* External clock */
88 return ioread32(lvds->mmio + reg); in rcar_lvds_read()
93 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
[all …]
/linux-6.12.1/drivers/pwm/
Dpwm-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
59 * Each capture input can be programmed to detect rising-edge, falling-edge,
96 void __iomem *mmio; member
124 clk_rate = clk_get_rate(pc->pwm_clk); in sti_pwm_get_prescale()
126 dev_err(pc->dev, "failed to get clock rate\n"); in sti_pwm_get_prescale()
127 return -EINVAL; in sti_pwm_get_prescale()
131 * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1 in sti_pwm_get_prescale()
134 value *= pc->max_pwm_cnt + 1; in sti_pwm_get_prescale()
137 return -EINVAL; in sti_pwm_get_prescale()
[all …]
/linux-6.12.1/arch/arm/boot/dts/allwinner/
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]

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