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/linux-6.12.1/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,nvec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
26 - description: divider clock
27 - description: fast clock
29 clock-names:
32 - const: div-clk
33 - const: fast-clk
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
[all …]
/linux-6.12.1/arch/arm64/boot/dts/exynos/
Dexynos7885-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 etc0: etc0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
[all …]
/linux-6.12.1/drivers/net/mdio/
Dmdio-hisi-femac.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Hisilicon Fast Ethernet MDIO Bus Driver
8 #include <linux/clk.h>
24 struct clk *clk; member
32 return readl_poll_timeout(data->membase + MDIO_RWCTRL, in hisi_femac_mdio_wait_ready()
38 struct hisi_femac_mdio_data *data = bus->priv; in hisi_femac_mdio_read()
46 data->membase + MDIO_RWCTRL); in hisi_femac_mdio_read()
52 return readl(data->membase + MDIO_RO_DATA) & 0xFFFF; in hisi_femac_mdio_read()
58 struct hisi_femac_mdio_data *data = bus->priv; in hisi_femac_mdio_write()
67 data->membase + MDIO_RWCTRL); in hisi_femac_mdio_write()
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/linux-6.12.1/drivers/bus/
Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
73 * FAST CSn CFG
[all …]
/linux-6.12.1/drivers/i2c/busses/
Di2c-stm32f4.c1 // SPDX-License-Identifier: GPL-2.0
13 * This driver is based on i2c-st.c
17 #include <linux/clk.h>
31 #include "i2c-stm32.h"
97 * struct stm32f4_i2c_msg - client specific data
98 * @addr: 8-bit target addr, including r/w bit
113 * struct stm32f4_i2c_dev - private data of the controller
118 * @clk: hw i2c clock
119 * @speed: I2C clock frequency of the controller. Standard or Fast are supported
128 struct clk *clk; member
[all …]
Di2c-designware-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
187 struct clk;
192 * struct dw_i2c_dev - private i2c-designware data
199 * @clk: input reference clock
225 * @rx_outstanding: current master-rx elements in tx fifo
230 * @fs_hcnt: fast speed HCNT value
231 * @fs_lcnt: fast speed LCNT value
232 * @fp_hcnt: fast plus HCNT value
233 * @fp_lcnt: fast plus LCNT value
239 * -1 if there is no semaphore.
[all …]
Di2c-uniphier-f.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
82 struct clk *clk; member
99 * TX-FIFO stores target address in it for the first access. in uniphier_fi2c_fill_txfifo()
103 fifo_space--; in uniphier_fi2c_fill_txfifo()
105 while (priv->len) { in uniphier_fi2c_fill_txfifo()
106 if (fifo_space-- <= 0) in uniphier_fi2c_fill_txfifo()
109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
110 priv->len--; in uniphier_fi2c_fill_txfifo()
116 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? in uniphier_fi2c_drain_rxfifo()
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Di2c-rk3x.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/clk.h>
83 * struct i2c_spec_values - I2C specification values for various modes
87 * @min_setup_start_ns: min set-up time for a repeated START conditio
89 * @min_data_setup_ns: min data set-up time
90 * @min_setup_stop_ns: min set-up time for STOP condition
139 * struct rk3x_i2c_calced_timings - calculated V1 timings
162 * struct rk3x_i2c_soc_data - SOC-specific data
173 * struct rk3x_i2c - private data of the controller
178 * @clk: function clk for rk3399 or function & Bus clks for others
[all …]
Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
11 * - The memory bus only supports 32-bit accesses.
12 * - A register must be configured for the I2C speed mode;
20 #include <linux/clk.h>
34 #define DRIVER_NAME "nmk-i2c"
73 #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */
74 #define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */
87 /* Baud-rate counter register (BRCR) */
88 #define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */
[all …]
Di2c-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
8 * based on a (non-working) driver which was:
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #include <linux/dma-mapping.h>
27 #include <linux/dma/mxs-dma.h>
29 #define DRIVER_NAME "mxs-i2c"
69 #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
71 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
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Di2c-pasemi-platform.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
16 #include "i2c-pasemi-core.h"
20 struct clk *clk_ref;
27 unsigned long clk_rate = clk_get_rate(data->clk_ref); in pasemi_platform_i2c_calc_clk_div()
30 return -EINVAL; in pasemi_platform_i2c_calc_clk_div()
32 data->smbus.clk_div = DIV_ROUND_UP(clk_rate, 16 * frequency); in pasemi_platform_i2c_calc_clk_div()
33 if (data->smbus.clk_div < 4) in pasemi_platform_i2c_calc_clk_div()
34 return dev_err_probe(data->smbus.dev, -EINVAL, in pasemi_platform_i2c_calc_clk_div()
35 "Bus frequency %d is too fast.\n", in pasemi_platform_i2c_calc_clk_div()
[all …]
Di2c-tegra.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-tegra.c
11 #include <linux/clk.h>
14 #include <linux/dma-mapping.h>
51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
154 * @MSG_END_REPEAT_START: Send repeat-start.
155 * @MSG_END_CONTINUE: Don't send stop or repeat-start.
[all …]
Di2c-meson.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
68 * struct meson_i2c - Meson I2C device private data
73 * @clk: Pointer to clock structure
90 struct clk *clk; member
116 data = readl(i2c->regs + reg); in meson_i2c_set_mask()
119 writel(data, i2c->regs + reg); in meson_i2c_set_mask()
124 i2c->tokens[0] = 0; in meson_i2c_reset_tokens()
125 i2c->tokens[1] = 0; in meson_i2c_reset_tokens()
126 i2c->num_tokens = 0; in meson_i2c_reset_tokens()
[all …]
Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
71 /* FAST MODE frequency */
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
84 /* calculate the value of CS bits in CCR register on fast mode */
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
89 /* calculate the value of CS bits in CSR register on fast mode */
95 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \
[all …]
/linux-6.12.1/drivers/spi/
Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
12 #include <linux/clk.h>
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
34 struct clk *clk; member
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
[all …]
/linux-6.12.1/arch/arm/boot/dts/qcom/
Dqcom-apq8026-lg-lenok.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include "qcom-msm8226.dtsi"
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
12 /delete-node/ &adsp_region;
17 chassis-type = "watch";
18 qcom,board-id = <132 0x0a>;
19 qcom,msm-id = <199 0x20000>;
27 stdout-path = "serial0:115200n8";
30 reserved-memory {
[all …]
Dqcom-msm8974-sony-xperia-rhine.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-msm8974.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 stdout-path = "serial0:115200n8";
18 gpio-keys {
19 compatible = "gpio-keys";
21 pinctrl-names = "default";
22 pinctrl-0 = <&gpio_keys_pin_a>;
[all …]
Dqcom-msm8974pro-fairphone-fp2.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-msm8974pro.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
12 chassis-type = "handset";
21 stdout-path = "serial0:115200n8";
24 gpio-keys {
25 compatible = "gpio-keys";
27 pinctrl-names = "default";
[all …]
/linux-6.12.1/drivers/clk/at91/
Dclk-h32mx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-h32mx.c
7 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <linux/clk-provider.h>
12 #include <linux/clk/at91_pmc.h>
34 regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr); in clk_sama5d4_h32mx_recalc_rate()
39 pr_warn("H32MX clock is too fast\n"); in clk_sama5d4_h32mx_recalc_rate()
54 if (rate - div < *parent_rate - rate) in clk_sama5d4_h32mx_round_rate()
67 return -EINVAL; in clk_sama5d4_h32mx_set_rate()
72 regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR, in clk_sama5d4_h32mx_set_rate()
[all …]
/linux-6.12.1/drivers/clocksource/
Dtimer-pistachio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pistachio clocksource based on general-purpose timers
10 #include <linux/clk.h>
80 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
81 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
82 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
83 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
99 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
105 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
114 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable()
[all …]
Dtimer-fttmr010.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
81 * - aspeed timer overflow interrupt is controlled by bits in Control
83 * - aspeed timers always generate interrupt when either one of the
113 * fast and stateless
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
129 return ~readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_down()
[all …]
/linux-6.12.1/arch/arm/boot/dts/aspeed/
Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
[all …]
/linux-6.12.1/drivers/input/misc/
Dadxl34x-spi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ADLX345/346 Three-Axis Digital Accelerometers (SPI Interface)
72 /* don't exceed max specified SPI CLK frequency */ in adxl34x_spi_probe()
73 if (spi->max_speed_hz > MAX_SPI_FREQ_HZ) { in adxl34x_spi_probe()
74 dev_err(&spi->dev, "SPI CLK %d Hz too fast\n", spi->max_speed_hz); in adxl34x_spi_probe()
75 return -EINVAL; in adxl34x_spi_probe()
78 ac = adxl34x_probe(&spi->dev, spi->irq, in adxl34x_spi_probe()
79 spi->max_speed_hz > MAX_FREQ_NO_FIFODELAY, in adxl34x_spi_probe()
102 MODULE_DESCRIPTION("ADXL345/346 Three-Axis Digital Accelerometer SPI Bus Driver");
/linux-6.12.1/arch/arm/kernel/
Dsmp_twd.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
28 static struct clk *twd_clk;
37 static int twd_shutdown(struct clock_event_device *clk) in twd_shutdown() argument
43 static int twd_set_oneshot(struct clock_event_device *clk) in twd_set_oneshot() argument
51 static int twd_set_periodic(struct clock_event_device *clk) in twd_set_periodic() argument
94 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_stop() local
96 twd_shutdown(clk); in twd_timer_stop()
97 disable_percpu_irq(clk->irq); in twd_timer_stop()
118 * frequency. The timer is local to a cpu, so cross-call to the in twd_rate_change()
[all …]

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