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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dti,tlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
[all …]
Dcs35l34.txt5 - compatible : "cirrus,cs35l34"
7 - reg : the I2C address of the device for I2C.
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-vtge-millivolt : Boost Voltage Value. Configures the boost
17 - cirrus,boost-nanohenry: Inductor value for boost converter. The value is
22 - reset-gpios: GPIO used to reset the amplifier.
24 - interrupts : IRQ line info CS35L34.
25 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
28 - cirrus,boost-peak-milliamp : Boost converter peak current limit in mA. The
32 - cirrus,i2s-sdinloc : ADSP SDIN I2S channel location. Indicates whether the
[all …]
/linux-6.12.1/drivers/irqchip/
Dqcom-pdc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
45 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
88 __pdc_enable_intr(d->hwirq, on); in pdc_enable_intr()
105 * GIC does not handle falling edge or active low. To allow falling edge and
106 * active low interrupts to be handled at GIC, PDC has an inverter that inverts
107 * falling edge into a rising edge and active low into an active high.
110 * Level sensitive active low LOW
111 * Rising edge sensitive NOT USED
112 * Falling edge sensitive LOW
[all …]
Dirq-aspeed-vic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
7 * Based on irq-vic.c:
9 * Copyright (C) 1999 - 2003 ARM Limited
32 * register set that interleaves "high" and "low". The offsets
33 * below are for the "low" register, add 4 to get to the high one
63 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); in vic_init_hw()
64 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); in vic_init_hw()
67 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); in vic_init_hw()
68 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); in vic_init_hw()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/power/reset/
Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
24 active->inactive edge, triggering negative edge triggered reset. After a delay specified by
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dcavium-octeon-gpio.txt4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
23 4 - level triggered active high.
24 8 - level triggered active low.
[all …]
Dnvidia,tegra20-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
/linux-6.12.1/drivers/media/dvb-frontends/
Dm88ds3103.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
52 * @ts_clk_pol: TS clk polarity. 1-active at falling edge; 0-active at rising
53 * edge.
59 * @lnb_hv_pol: LNB H/V pin polarity. 0: pin high set to VOLTAGE_18, pin low to
60 * set VOLTAGE_13. 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18.
61 * @lnb_en_pol: LNB enable pin polarity. 0: pin high to disable, pin low to
62 * enable. 1: pin high to enable, pin low to disable.
88 * struct m88ds3103_config - m88ds3102 configuration
[all …]
/linux-6.12.1/drivers/iio/common/st_sensors/
Dst_sensors_trigger.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 STMicroelectronics Inc.
19 * st_sensors_new_samples_available() - check if more samples came in
24 * false - no new samples available or read error
25 * true - new samples available
33 if (!sdata->sensor_settings->drdy_irq.stat_drdy.addr) in st_sensors_new_samples_available()
37 if (!indio_dev->active_scan_mask) in st_sensors_new_samples_available()
40 ret = regmap_read(sdata->regmap, in st_sensors_new_samples_available()
41 sdata->sensor_settings->drdy_irq.stat_drdy.addr, in st_sensors_new_samples_available()
44 dev_err(indio_dev->dev.parent, in st_sensors_new_samples_available()
[all …]
/linux-6.12.1/drivers/media/rc/
Dserial_ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * serial_ir - Device driver that records pulse- and pause-lengths
6 * (space-lengths) between DDCD event on a serial port.
8 * Copyright (C) 1996,97 Ralph Metzler <rjkm@thp.uni-koeln.de>
13 * Copyright (C) 2016 Sean Young <sean@mess.org> (port to rc-core)
28 #include <media/rc-core.h>
37 void (*send_pulse)(unsigned int length, ktime_t edge);
56 static int sense = -1; /* -1 = auto, 0 = active high, 1 = active low */
57 static bool txsense; /* 0 = active high, 1 = active low */
60 static void send_pulse_irdeo(unsigned int length, ktime_t edge);
[all …]
/linux-6.12.1/Documentation/arch/arm/pxa/
Dmfp.rst7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
26 | +---------+
27 +--------+ +------>| |
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/panel/
Dpanel-timing.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
30 core_intc: core-interrupt-controller {
[all …]
Dnxp,lpc3220-mic.txt4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
/linux-6.12.1/drivers/staging/greybus/
Daudio_apbridgea.h1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (c) 2015-2016 Google Inc.
8 * we can predefine several low-level attributes of the communication
11 * - there are two channels (i.e., stereo)
12 * - the low-level protocol is I2S as defined by Philips/NXP
13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
15 * - WCLK low for left channel; high for right channel
16 * - TX data is sent on the falling edge of BCLK
17 * - RX data is received/latched on the rising edge of BCLK
/linux-6.12.1/drivers/clk/
Dclk-axi-clkgen.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
10 #include <linux/clk-provider.h>
143 d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); in axi_clkgen_calc_params()
144 d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()
147 fvco_min_fract = limits->fvco_min << fract_shift; in axi_clkgen_calc_params()
148 fvco_max_fract = limits->fvco_max << fract_shift; in axi_clkgen_calc_params()
163 if (abs(f - fout) < abs(best_f - fout)) { in axi_clkgen_calc_params()
166 *best_m = m << (3 - fract_shift); in axi_clkgen_calc_params()
[all …]
/linux-6.12.1/Documentation/input/devices/
Drotary-encoder.rst2 rotary-encoder - a generic driver for GPIO connected devices
8 --------
11 peripherals with two wires. The outputs are phase-shifted by 90 degrees
15 Some encoders have both outputs low in stable states, others also have
16 a stable state with both outputs high (half-period mode) and some have
17 a stable state in all steps (quarter-period mode).
33 |<-------->|
36 |<-->|
37 one step (half-period mode)
40 one step (quarter-period mode)
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
6 The device uses the standard MicroWire half-duplex transfer timing.
7 Master output is set on low clock and sensed by the RTC on the rising
8 edge. Master input is set by the RTC on the trailing edge and is sensed
9 by the master on low clock.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
[all …]
/linux-6.12.1/kernel/irq/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 # Print level/edge extra information
50 # Edge style eoi based handler (cell)
59 # Generic irq_domain hw <--> linux irq number translation
74 # Support for obsolete non-mapping irq domains
79 # Support for hierarchical fasteoi+edge and fasteoi+level handlers
125 low kernel memory footprint on smaller machines.
128 out the interrupt descriptors in a more NUMA-friendly way. )
149 Allow to specify the low level IRQ handler at run time.
/linux-6.12.1/drivers/staging/sm750fb/
Dddk750_sii164.c1 // SPDX-License-Identifier: GPL-2.0
79 * edge_select - Edge Select:
80 * 0 = Input data is falling edge latched (falling
81 * edge latched first in dual edge mode)
82 * 1 = Input data is rising edge latched (rising
83 * edge latched first in dual edge mode)
84 * bus_select - Input Bus Select:
85 * 0 = Input data bus is 12-bits wide
86 * 1 = Input data bus is 24-bits wide
87 * dual_edge_clk_select - Dual Edge Clock Select
[all …]
/linux-6.12.1/drivers/pinctrl/
Dpinctrl-at91.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
45 #define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
46 #define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
[all …]
/linux-6.12.1/Documentation/core-api/
Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
51 This split implementation of high-level IRQ handlers allows us to
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/rtc/
Dmaxim-ds1302.txt1 * Maxim/Dallas Semiconductor DS-1302 RTC
5 The device uses the standard MicroWire half-duplex transfer timing.
6 Master output is set on low clock and sensed by the RTC on the rising
7 edge. Master input is set by the RTC on the trailing edge and is sensed
8 by the master on low clock.
12 - compatible : Should be "maxim,ds1302"
16 - reg : Should be address of the device chip select within
19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
22 - spi-3wire : The device has a shared signal IN/OUT line.
24 - spi-lsb-first : DS-1302 requires least significant bit first
[all …]

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