fsl/cpm_qe/fsl%2Cqe-tsa.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10   - Herve Codina <herve.codina@bootlin.com>
13   The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14   Its purpose is to route some TDM time-slots to other internal serial
20       - enum:
21           - fsl,mpc8321-tsa
22       - const: fsl,qe-tsa
26       - description: SI (Serial Interface) register base
27       - description: SI RAM base
29   reg-names:
31       - const: si_regs
32       - const: si_ram
34   '#address-cells':
37   '#size-cells':
41   '^tdm@[0-3]$':
56       fsl,common-rxtx-pins:
61           Without the 'fsl,common-rxtx-pins' property, the four pins are used.
62           With the 'fsl,common-rxtx-pins' property, two pins are used.
67           - description: Receive sync clock
68           - description: Receive data clock
69           - description: Transmit sync clock
70           - description: Transmit data clock
72       clock-names:
75           - const: rsync
76           - const: rclk
77           - const: tsync
78           - const: tclk
80       fsl,rx-frame-sync-delay-bits:
88       fsl,tx-frame-sync-delay-bits:
96       fsl,clock-falling-edge:
99           Data is sent on falling edge of the clock (and received on the rising
100           edge). If not present, data is sent on the rising edge (and received
101           on the falling edge).
103       fsl,fsync-rising-edge:
106           Frame sync pulses are sampled with the rising edge of the channel
107           clock. If not present, pulses are sampled with the falling edge.
109       fsl,fsync-active-low:
112           Frame sync signals are active on low logic level.
115       fsl,double-speed-clock:
121       '^fsl,[rt]x-ts-routes$':
122         $ref: /schemas/types.yaml#/definitions/uint32-matrix
124           A list of tuple that indicates the Tx or Rx time-slots routes.
127             - description:
128                 The number of time-slots
131             - description: |
133                 (dt-bindings/soc/qe-fsl,tsa.h defines these values)
134                  - 0: No destination
135                  - 1: UCC1
136                  - 2: UCC2
137                  - 3: UCC3
138                  - 4: UCC4
139                  - 5: UCC5
145       # If fsl,common-rxtx-pins is present, only 2 clocks are needed.
147       - if:
149             - fsl,common-rxtx-pins
154             clock-names:
160             clock-names:
164       - reg
165       - clocks
166       - clock-names
169   - compatible
170   - reg
171   - reg-names
172   - '#address-cells'
173   - '#size-cells'
178   - |
179     #include <dt-bindings/soc/qe-fsl,tsa.h>
182         compatible = "fsl,mpc8321-tsa", "fsl,qe-tsa";
185         reg-names = "si_regs", "si_ram";
187         #address-cells = <1>;
188         #size-cells = <0>;
195             clock-names = "rsync", "rclk";
197             fsl,common-rxtx-pins;
198             fsl,fsync-rising-edge;
200             fsl,tx-ts-routes = <2 0>,             /* TS 0..1 */
205             fsl,rx-ts-routes = <2 0>,             /* TS 0..1 */