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/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
10 #include <linux/clk-provider.h>
43 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3
51 * internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0]
55 /* Controls whether the RXEN and RXD[3:0] signals should be aligned with the
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
65 /* Adjusts the skew between each bit of RXEN and RXD[3:0]. If a signal has a
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
[all …]
Ddwmac-imx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8
33 #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
34 #define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
70 struct imx_priv_data *dwmac = plat_dat->bsp_priv; in imx8mp_set_intf_mode() local
73 switch (plat_dat->mac_interface) { in imx8mp_set_intf_mode()
79 val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL); in imx8mp_set_intf_mode()
89 pr_debug("imx dwmac doesn't support %d interface\n", in imx8mp_set_intf_mode()
90 plat_dat->mac_interface); in imx8mp_set_intf_mode()
91 return -EINVAL; in imx8mp_set_intf_mode()
[all …]
Ddwmac-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
43 * ------------------------------------------------
46 * ------------------------------------------------
48 *| | clk-125/txclk | txclk |
49 * ------------------------------------------------
51 *| | clk-125/txclk | clkgen |
53 * ------------------------------------------------
55 *| | |clkgen/phyclk-in |
[all …]
Ddwmac-loongson1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Loongson-1 DWMAC glue layer
5 * Copyright (C) 2011-2023 Keguang Zhang <keguang.zhang@gmail.com>
21 /* Loongson-1 SYSCON Registers */
25 /* Loongson-1B SYSCON Register Bits */
27 #define GMAC1_USE_UART0 BIT(3)
32 #define GMAC1_USE_TXCLK BIT(3)
37 /* Loongson-1C SYSCON Register Bits */
51 struct ls1x_dwmac *dwmac = priv; in ls1b_dwmac_syscon_init() local
52 struct plat_stmmacenet_data *plat = dwmac->plat_dat; in ls1b_dwmac_syscon_init()
[all …]
Ddwmac-visconti.c1 // SPDX-License-Identifier: GPL-2.0
24 #define ETHER_CLK_SEL_RMII_CLK_RST BIT(3)
59 struct visconti_eth *dwmac = priv; in visconti_eth_fix_mac_speed() local
60 struct net_device *netdev = dev_get_drvdata(dwmac->dev); in visconti_eth_fix_mac_speed()
64 spin_lock_irqsave(&dwmac->lock, flags); in visconti_eth_fix_mac_speed()
67 val = readl(dwmac->reg + MAC_CTRL_REG); in visconti_eth_fix_mac_speed()
72 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) in visconti_eth_fix_mac_speed()
76 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) in visconti_eth_fix_mac_speed()
78 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII) in visconti_eth_fix_mac_speed()
83 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) in visconti_eth_fix_mac_speed()
[all …]
Ddwmac-ingenic.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwmac-ingenic.c - Ingenic SoCs DWMAC specific glue layer
36 #define MACPHYC_SOFT_RST_MASK GENMASK(3, 3)
75 struct ingenic_mac *mac = plat_dat->bsp_priv; in ingenic_mac_init()
78 if (mac->soc_info->set_mode) { in ingenic_mac_init()
79 ret = mac->soc_info->set_mode(plat_dat); in ingenic_mac_init()
89 struct ingenic_mac *mac = plat_dat->bsp_priv; in jz4775_mac_set_mode()
92 switch (plat_dat->mac_interface) { in jz4775_mac_set_mode()
96 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n"); in jz4775_mac_set_mode()
102 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n"); in jz4775_mac_set_mode()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
17 # We need a select here so we don't match all nodes with 'snps,dwmac'
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
[all …]
Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson DWMAC Ethernet controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
[all …]
Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: StarFive JH7110 DWMAC glue layer
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
[all …]
Dnxp,dwmac-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8/9 DWMAC glue layer
10 - Clark Wang <xiaoning.wang@nxp.com>
11 - Shawn Guo <shawnguo@kernel.org>
12 - NXP Linux Team <linux-imx@nxp.com>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - nxp,imx8mp-dwmac-eqos
[all …]
Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
[all …]
Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel DWMAC glue layer
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
[all …]
Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DWMAC glue layer controller
10 - Biao Huang <biao.huang@mediatek.com>
15 # We need a select here so we don't match all nodes with 'snps,dwmac'
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
[all …]
Dqcom,ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
17 - $ref: snps,dwmac.yaml#
22 - qcom,qcs404-ethqos
23 - qcom,sa8775p-ethqos
24 - qcom,sc8280xp-ethqos
25 - qcom,sm8150-ethqos
30 reg-names:
[all …]
/linux-6.12.1/arch/arm64/boot/dts/st/
Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dstm32mp133.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
14 reg-names = "m_can", "message_ram";
17 interrupt-names = "int0", "int1";
19 clock-names = "hclk", "cclk";
20 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
27 reg-names = "m_can", "message_ram";
30 interrupt-names = "int0", "int1";
32 clock-names = "hclk", "cclk";
33 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Dmeson-s4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/meson-s4-gpio.h>
10 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
12 #include <dt-bindings/power/meson-s4-power.h>
13 #include <dt-bindings/reset/amlogic,meson-s4-reset.h>
17 #address-cells = <2>;
[all …]
Damlogic-c3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/amlogic,c3-reset.h>
10 #include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
12 #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
13 #include <dt-bindings/power/amlogic,c3-pwrc.h>
14 #include <dt-bindings/gpio/amlogic-c3-gpio.h>
[all …]
/linux-6.12.1/arch/arm/boot/dts/axis/
Dartpec6-devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 // Axis ARTPEC-6 development board.
4 /dts-v1/;
8 model = "ARTPEC-6 development board";
9 compatible = "axis,artpec6-dev-board", "axis,artpec6";
19 stdout-path = "serial3:115200n8";
51 phy-handle = <&phy1>;
52 phy-mode = "gmii";
55 #address-cells = <0x1>;
56 #size-cells = <0x0>;
[all …]
/linux-6.12.1/arch/arc/boot/dts/
Dabilis_tb10x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
29 interrupts = <3>;
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsa8775p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include "sa8775p-ride.dtsi"
12 compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
16 phy-mode = "sgmii";
20 phy-mode = "sgmii";
24 compatible = "snps,dwmac-mdio";
25 #address-cells = <1>;
26 #size-cells = <0>;
29 compatible = "ethernet-phy-id0141.0dd4";
[all …]
Dsa8775p-ride-r3.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include "sa8775p-ride.dtsi"
12 compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p";
16 phy-mode = "2500base-x";
20 phy-mode = "2500base-x";
24 compatible = "snps,dwmac-mdio";
25 #address-cells = <1>;
26 #size-cells = <0>;
29 compatible = "ethernet-phy-id31c3.1c33";
[all …]
/linux-6.12.1/arch/mips/boot/dts/loongson/
Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
[all …]

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