| /linux-6.12.1/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 31 * R0 : DLL ctrl value pre-Sleep
36 * when we get called, but the DLL probably isn't. We will wait a bit more in
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
48 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
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| D | sram243x.S | 45 /* dll lock mode */
52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
55 bl i_dll_wait @ wait for dll to lock
57 /* get dll value */
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
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| D | sram242x.S | 45 /* dll lock mode */
52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
55 bl i_dll_wait @ wait for dll to lock
57 /* get dll value */
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
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| D | sdrc2xxx.c | 30 /* Memory timing, DLL mode flags */
56 * Check the DLL lock state, and return tue if running in unlock mode.
57 * This is needed to compensate for the shifted DLL value in unlock mode.
131 /* With DDR we need to determine the low frequency DLL value */ in omap2xxx_sdrc_init_params()
148 /* set fast timings with DLL filter disabled */ in omap2xxx_sdrc_init_params()
162 /* 90 degree phase for anything below 133MHz + disable DLL filter */ in omap2xxx_sdrc_init_params()
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| /linux-6.12.1/include/soc/at91/ |
| D | sama7-ddr.h | 16 #define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
18 #define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
19 #define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */
29 #define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
30 #define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */
49 #define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register */
50 #define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register */
51 #define DDR3PHY_DXDLLCR_DLLDIS (1 << 31) /* DLL Disable */
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| /linux-6.12.1/Documentation/devicetree/bindings/mmc/ |
| D | hisilicon,hi3798cv200-dw-mshc.yaml | 38 hisilicon,sap-dll-reg:
41 DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path.
45 - description: Sample DLL register offset in CRG address space
64 - hisilicon,sap-dll-reg
67 hisilicon,sap-dll-reg: false
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| D | cdns,sdhci.yaml | 34 # PHY DLL input delays:
84 # PHY DLL clock delays:
92 cdns,phy-dll-delay-sdclk:
100 cdns,phy-dll-delay-sdclk-hsmmc:
108 cdns,phy-dll-delay-strobe:
155 cdns,phy-dll-delay-sdclk = <0>;
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| D | fsl-imx-esdhc.yaml | 113 This is used to set the clock delay for DLL(Delay Line) on override mode
116 chapter, DLL (Delay Line) section in RM for details.
148 fsl,strobe-dll-delay-target:
151 Specify the strobe dll control slave delay target.
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| /linux-6.12.1/arch/x86/boot/ |
| D | early_serial_console.c | 21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
104 unsigned char lcr, dll, dlh; in probe_baud() local
109 dll = inb(port + DLL); in probe_baud()
112 quot = (dlh << 8) | dll; in probe_baud()
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| /linux-6.12.1/drivers/phy/intel/ |
| D | phy-intel-keembay-emmc.c | 76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
131 /* Set the frequency of the DLL operation */ in keembay_emmc_phy_power()
135 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in keembay_emmc_phy_power()
139 /* Turn on the DLL */ in keembay_emmc_phy_power()
143 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in keembay_emmc_phy_power()
148 * We turned on the DLL even though the rate was 0 because we the in keembay_emmc_phy_power()
149 * clock might be turned on later. ...but we can't wait for the DLL in keembay_emmc_phy_power()
160 * After enabling analog DLL circuits docs say that we need 10.2 us if in keembay_emmc_phy_power()
168 * NOTE: There appear to be corner cases where the DLL seems to take in keembay_emmc_phy_power()
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| D | phy-intel-lgm-emmc.c | 110 /* Set the frequency of the DLL operation */ in intel_emmc_phy_power()
114 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in intel_emmc_phy_power()
118 /* Turn on the DLL */ in intel_emmc_phy_power()
122 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in intel_emmc_phy_power()
127 * After enabling analog DLL circuits docs say that we need 10.2 us if in intel_emmc_phy_power()
135 * NOTE: There appear to be corner cases where the DLL seems to take in intel_emmc_phy_power()
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| /linux-6.12.1/arch/powerpc/kernel/ |
| D | udbg_16550.c | 97 unsigned int dll, base_bauds; in udbg_uart_setup() local
108 dll = base_bauds / speed; in udbg_uart_setup()
114 udbg_uart_out(UART_DLL, dll & 0xff); in udbg_uart_setup()
115 udbg_uart_out(UART_DLM, dll >> 8); in udbg_uart_setup()
126 unsigned int dll, dlm, divisor, prescaler, speed; in udbg_probe_uart_speed() local
135 dll = udbg_uart_in(UART_DLL); in udbg_probe_uart_speed()
137 divisor = dlm << 8 | dll; in udbg_probe_uart_speed()
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| /linux-6.12.1/drivers/phy/rockchip/ |
| D | phy-rockchip-emmc.c | 150 * pretty spot on for the DLL range, so warn if we're too in rockchip_emmc_phy_power()
186 /* Set the frequency of the DLL operation */ in rockchip_emmc_phy_power()
192 /* Turn on the DLL */ in rockchip_emmc_phy_power()
200 * We turned on the DLL even though the rate was 0 because we the in rockchip_emmc_phy_power()
201 * clock might be turned on later. ...but we can't wait for the DLL in rockchip_emmc_phy_power()
212 * After enabling analog DLL circuits docs say that we need 10.2 us if in rockchip_emmc_phy_power()
220 * NOTE: There appear to be corner cases where the DLL seems to take in rockchip_emmc_phy_power()
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| /linux-6.12.1/drivers/mmc/host/ |
| D | sdhci-esdhc.h | 89 /* DLL Config 0 Register */
95 /* DLL Config 1 Register */
99 /* DLL Status 0 Register */
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| D | dw_mmc-hi3798mv200.c | 25 /* DLL ctrl reg */
114 * It needs special interaction with the DLL. in dw_mci_hi3798mv200_execute_tuning_mix_mode()
202 priv->crg_reg = syscon_regmap_lookup_by_phandle(np, "hisilicon,sap-dll-reg"); in dw_mci_hi3798mv200_init()
207 ret = of_property_read_u32_index(np, "hisilicon,sap-dll-reg", 1, &priv->sap_dll_offset); in dw_mci_hi3798mv200_init()
209 return dev_err_probe(host->dev, ret, "failed to get sample DLL register offset\n"); in dw_mci_hi3798mv200_init()
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| D | sdhci-pci-o2micro.c | 187 * This function is used to detect dll lock status.
188 * Since the dll lock status bit will toggle randomly
238 * This function is used to fix o2 dll shift issue.
281 * need wait at least 5ms for dll status stable, in sdhci_o2_dll_recovery()
291 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", in sdhci_o2_dll_recovery()
304 pr_err("%s: DLL adjust over max times\n", in sdhci_o2_dll_recovery()
361 /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ in sdhci_o2_execute_tuning()
382 /* wait DLL lock, timeout value 5ms */ in sdhci_o2_execute_tuning()
385 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", in sdhci_o2_execute_tuning()
388 * Judge the tuning reason, whether caused by dll shift in sdhci_o2_execute_tuning()
[all …]
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| D | sdhci-msm.c | 450 * Write the selected DLL clock output phase (0 ... 15) in msm_config_cm_dll_phase()
474 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", in msm_config_cm_dll_phase()
483 * DLL clock output phases that can be used as sampling
487 * Select the 3/4 of the range and configure the DLL with the
488 * selected DLL clock output phase.
623 /* Initialize the DLL (Programmable Delay Line) */
641 * Make sure that clock is always enabled when DLL in msm_init_cm_dll()
703 /* wait for 5us before enabling DLL clock */ in msm_init_cm_dll()
730 * Configure DLL user control register to enable DLL status. in msm_init_cm_dll()
767 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", in msm_init_cm_dll()
[all …]
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| D | sdhci-of-dwcmshc.c | 176 /* PHY DLL control settings */
178 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */
179 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */
181 /* PHY DLL configuration register 1 */
184 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */
185 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */
187 /* PHY DLL configuration register 2 */
189 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */
191 /* PHY DLL master and slave delay line configuration settings */
378 /* enable phy dll */ in dwcmshc_phy_1_8v_init()
[all …]
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| D | sdhci-xenon-phy.c | 128 /* Offset of DLL Control register */
132 /* DLL Update Enable bit */
346 * Enable eMMC PHY HW DLL
347 * DLL should be enabled and stable before HS200/SDR104 tuning,
365 /* Enable DLL */ in xenon_emmc_phy_enable_dll()
394 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n"); in xenon_emmc_phy_enable_dll()
404 * Enable HW DLL and set the TUNING_STEP
421 /* Achieve TUNING_STEP with HW DLL help */ in xenon_emmc_phy_config_tuning()
491 * 3. DLL is enabled in xenon_emmc_phy_strobe_delay_adj()
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| /linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
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| D | sddr2.c | 63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
69 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr2_calc()
98 ram->mr[1] |= !DLL; in nvkm_sddr2_calc()
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| D | sddr3.c | 72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
115 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
110 Note: if DLL was bypassed, the odt will also stop working.
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
117 is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
118 Note: PHY DLL and PHY ODT are independent.
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| /linux-6.12.1/drivers/tty/serial/8250/ |
| D | 8250_pxa.c | 65 unsigned int dll; in serial_pxa_dl_write() local
72 dll = serial_in(up, UART_DLL); in serial_pxa_dl_write()
73 WARN_ON(dll != (value & 0xff)); in serial_pxa_dl_write()
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| /linux-6.12.1/drivers/net/ethernet/cavium/thunder/ |
| D | thunder_xcv.c | 69 /* Take DLL out of reset */ in xcv_init_hw()
78 /* Wait for DLL to lock */ in xcv_init_hw()
81 /* Configure DLL - enable or bypass in xcv_init_hw()
|