Lines Matching full:dll

176 /* PHY DLL control settings */
178 #define PHY_DLL_CTRL_DISABLE		0x0 /* PHY DLL is enabled */
179 #define PHY_DLL_CTRL_ENABLE		0x1 /* PHY DLL is disabled */
181 /* PHY DLL  configuration register 1 */
184 #define PHY_DLL_CNFG1_SLVDLY		0x2 /* DLL slave update delay input */
185 #define PHY_DLL_CNFG1_WAITCYCLE		0x5 /* DLL wait cycle input */
187 /* PHY DLL configuration register 2 */
189 #define PHY_DLL_CNFG2_JUMPSTEP		0xa /* DLL jump step input */
191 /* PHY DLL master and slave delay line configuration settings */
378 	/* enable phy dll */  in dwcmshc_phy_1_8v_init()
425 	/* enable phy dll */  in dwcmshc_phy_3_3v_init()
640 		 * Disable DLL and reset both of sample and drive clock.  in dwcmshc_rk3568_set_clock()
641 		 * The bypass bit and start bit need to be set if DLL is not locked.  in dwcmshc_rk3568_set_clock()
659 	/* Reset DLL */  in dwcmshc_rk3568_set_clock()
673 	/* Init DLL settings */  in dwcmshc_rk3568_set_clock()
682 		dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");  in dwcmshc_rk3568_set_clock()
780 	 * cannot use DLL for this condition.  in dwcmshc_rk35xx_postinit()