| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/ |
| D | uncore-ddrc.json | 5 "BriefDescription": "DDRC total write operations",
6 "PublicDescription": "DDRC total write operations",
7 "Unit": "hisi_sccl,ddrc"
12 "BriefDescription": "DDRC total read operations",
13 "PublicDescription": "DDRC total read operations",
14 "Unit": "hisi_sccl,ddrc"
19 "BriefDescription": "DDRC write commands",
20 "PublicDescription": "DDRC write commands",
21 "Unit": "hisi_sccl,ddrc"
26 "BriefDescription": "DDRC read commands",
[all …]
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| D | uncore-hha.json | 48 "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
49 "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
55 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
56 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
62 … "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
63 … "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
69 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
70 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | imx8m-ddrc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
20 The Linux driver for the DDRC doesn't even map registers (they're included
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
64 ddrc: memory-controller@3d400000 {
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | snps,dw-umctl2-ddrc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
28 const: snps,ddrc-3.80a
30 const: snps,dw-umctl2-ddrc
32 const: xlnx,zynqmp-ddrc-2.40a
36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
61 reference clock, DDRC core clock, Scrubber standalone clock
62 (synchronous to the DDRC clock).
96 compatible = "xlnx,zynqmp-ddrc-2.40a";
107 compatible = "snps,dw-umctl2-ddrc";
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| D | xlnx,zynq-ddrc-a05.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
20 const: xlnx,zynq-ddrc-a05
34 compatible = "xlnx,zynq-ddrc-a05";
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| /linux-6.12.1/Documentation/devicetree/bindings/interconnect/ |
| D | fsl,imx8m-noc.yaml | 53 fsl,ddrc:
81 fsl,ddrc = <&ddrc>;
96 ddrc: memory-controller@3d400000 {
97 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
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| /linux-6.12.1/drivers/perf/hisilicon/ |
| D | hisi_uncore_ddrc_pmu.c | 3 * HiSilicon SoC DDRC uncore Hardware event counters support
21 /* DDRC register definition in v1 */
37 /* DDRC register definition in v2 */
46 /* DDRC has 8-counters */
110 * For DDRC PMU v1, event has been mapped to fixed-purpose counter by hardware,
172 /* For DDRC PMU, we use event code as counter index */ in hisi_ddrc_pmu_v1_get_event_idx()
301 * Use the SCCL_ID and DDRC channel ID to identify the in hisi_ddrc_pmu_init_data()
302 * DDRC PMU, while SCCL_ID is in MPIDR[aff2]. in hisi_ddrc_pmu_init_data()
306 dev_err(&pdev->dev, "Can not read ddrc channel-id!\n"); in hisi_ddrc_pmu_init_data()
312 dev_err(&pdev->dev, "Can not read ddrc sccl-id!\n"); in hisi_ddrc_pmu_init_data()
[all …]
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| D | hisi_uncore_pmu.h | 103 /* For DDRC PMU v2: each DDRC has more than one DMC */
|
| /linux-6.12.1/tools/perf/pmu-events/arch/test/test_soc/cpu/ |
| D | uncore.json | 5 "BriefDescription": "DDRC write commands",
6 "PublicDescription": "DDRC write commands",
7 "Unit": "hisi_sccl,ddrc"
|
| /linux-6.12.1/arch/arm/mach-zynq/ |
| D | pm.c | 58 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); in zynq_pm_late_init()
60 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); in zynq_pm_late_init()
63 * Enable DDRC clock stop feature. The HW takes care of in zynq_pm_late_init()
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| /linux-6.12.1/drivers/power/reset/ |
| D | at91-sama5d2_shdwc.c | 89 struct ddrc_reg_config ddrc; member
271 .ddrc = {
288 .ddrc = {
386 if (at91_shdwc->rcfg->ddrc.type_mask) { in at91_shdwc_probe()
403 at91_shdwc->rcfg->ddrc.type_offset) & in at91_shdwc_probe()
404 at91_shdwc->rcfg->ddrc.type_mask; in at91_shdwc_probe()
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| /linux-6.12.1/Documentation/admin-guide/perf/ |
| D | hisi-pmu.rst | 6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
20 HHA and DDRC etc. The available events and configuration options shall
23 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
26 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
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| D | alibaba_pmu.rst | 28 based on DDRC core clock.
53 By counting the READ, WRITE and RMW commands sent to the DDRC through the HIF
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| /linux-6.12.1/drivers/devfreq/ |
| D | imx8m-ddrc.c | 262 dev_err(dev, "ddrc failed freq switch to %lu from %lu: error %d. now at %lu\n", in imx8m_ddrc_target()
265 dev_err(dev, "ddrc failed freq update to %lu from %lu, now at %lu\n", in imx8m_ddrc_target()
268 dev_dbg(dev, "ddrc freq set to %lu (was %lu)\n", in imx8m_ddrc_target()
441 { .compatible = "fsl,imx8m-ddrc", },
449 .name = "imx8m-ddrc-devfreq",
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| D | Makefile | 13 obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
|
| /linux-6.12.1/tools/perf/pmu-events/ |
| D | empty-pmu-events.c | 29 /* offset=570 */ "hisi_sccl,ddrc\000"
30 …set=585 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DD…
73 { 585 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDR…
100 .pmu_name = { 570 /* hisi_sccl,ddrc\000 */ },
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| /linux-6.12.1/drivers/interconnect/imx/ |
| D | imx8mn.c | 17 .phandle_name = "fsl,ddrc",
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| D | imx8mm.c | 20 .phandle_name = "fsl,ddrc",
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| D | imx8mq.c | 18 .phandle_name = "fsl,ddrc",
|
| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | imx8mm-evk.dts | 20 &ddrc {
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| D | imx8mn-ddr4-evk.dts | 32 &ddrc {
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| /linux-6.12.1/drivers/edac/ |
| D | synopsys_edac.c | 200 /* DDRC Software control register */
203 /* DDRC ECC CE & UE poison mask */
207 /* DDRC Device config masks */
974 .compatible = "xlnx,zynq-ddrc-a05",
978 .compatible = "xlnx,zynqmp-ddrc-2.40a",
982 .compatible = "snps,ddrc-3.80a",
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| /linux-6.12.1/arch/arm64/boot/dts/intel/ |
| D | socfpga_n5x_socdk.dts | 30 compatible = "snps,ddrc-3.80a";
|
| /linux-6.12.1/arch/mips/include/asm/mach-rc32434/ |
| D | ddr.h | 40 u32 ddrc; member
|
| /linux-6.12.1/tools/perf/tests/ |
| D | pmu-events.c | 132 .desc = "DDRC write commands",
134 .long_desc = "DDRC write commands",
135 .pmu = "hisi_sccl,ddrc",
138 .alias_long_desc = "DDRC write commands",
|