memory-controllers/fsl/imx8m-ddrc.yaml

4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
13   The DDRC block is integrated in i.MX8M for interfacing with DDR based
20   The Linux driver for the DDRC doesn't even map registers (they're included
28           - fsl,imx8mn-ddrc
29           - fsl,imx8mm-ddrc
30           - fsl,imx8mq-ddrc
31       - const: fsl,imx8m-ddrc
36       Base address and size of DDRC CTL area.
37       This is not currently mapped by the imx8m-ddrc driver.
64     ddrc: memory-controller@3d400000 {
65         compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";