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/linux-6.12.1/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Chen-Yu Tsai <wens@csie.org>
15 - Maxime Ripard <mripard@kernel.org>
20 - const: allwinner,sun4i-a10-hdmi
21 - const: allwinner,sun5i-a10s-hdmi
22 - const: allwinner,sun6i-a31-hdmi
23 - items:
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Dbrcm,bcm2711-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eric Anholt <eric@anholt.net>
15 - brcm,bcm2711-hdmi0
16 - brcm,bcm2711-hdmi1
20 - description: HDMI controller register range
21 - description: DVP register range
22 - description: HDMI PHY register range
[all …]
Dst,stih4xx.txt3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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Damlogic,meson-dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 - $ref: /schemas/sound/dai-common.yaml#
18 - A Synopsys DesignWare HDMI Controller IP
19 - A TOP control block controlling the Clocks and PHY
20 - A custom HDMI PHY in order to convert video to TMDS signal
27 |___________________________________|<=> DDC
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/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Dsynopsys,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Synopsys DesignWare HDMI TX Controller
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
26 reg-io-width:
36 - description: The bus clock for either AHB and APB
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/linux-6.12.1/Documentation/devicetree/bindings/display/rockchip/
Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DWC HDMI TX Encoder
10 - Mark Yao <markyao0591@gmail.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
18 - $ref: /schemas/sound/dai-common.yaml#
23 - rockchip,rk3228-dw-hdmi
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/linux-6.12.1/drivers/gpu/drm/bridge/
Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
243 /* LM DDC, default value: 0x80 */
252 /* DDC I2C Manual, default value: 0x03 */
263 /* DDC I2C Target Slave Address, default value: 0x00 */
267 /* DDC I2C Target Segment Address, default value: 0x00 */
270 /* DDC I2C Target Offset Address, default value: 0x00 */
273 /* DDC I2C Data In count #1, default value: 0x00 */
276 /* DDC I2C Data In count #2, default value: 0x00 */
280 /* DDC I2C Status, default value: 0x04 */
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/linux-6.12.1/Documentation/devicetree/bindings/display/samsung/
Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
19 - samsung,exynos4212-hdmi
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/linux-6.12.1/arch/arm/boot/dts/mediatek/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_aux.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
216 * 2.3.4 "Detailed uPacket TX AUX CH State Description".
225 * EPR #379763: by trial-and-error on different systems,
229 * AUX Error or AUX Timeout conditions - not during normal operation.
243 struct ddc *ddc; member
301 struct ddc *ddc);
303 int dce_aux_transfer_raw(struct ddc_service *ddc,
307 int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
310 bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
315 (struct ddc_service *ddc,
/linux-6.12.1/arch/arm/boot/dts/allwinner/
Dsun5i-a10s.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/dma/sun4i-a10.h>
55 #address-cells = <1>;
56 #size-cells = <1>;
59 framebuffer-lcd0-hdmi {
60 compatible = "allwinner,simple-framebuffer",
61 "simple-framebuffer";
62 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 display-engine {
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Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_lvds.c2 * Copyright © 2006-2007 Intel Corporation
63 int tx; member
108 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_lvds_get_hw_state()
113 wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain); in intel_lvds_get_hw_state()
117 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); in intel_lvds_get_hw_state()
119 intel_display_power_put(i915, encoder->power_domain, wakeref); in intel_lvds_get_hw_state()
127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_config()
131 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
133 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
143 crtc_state->hw.adjusted_mode.flags |= flags; in intel_lvds_get_config()
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/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/sound/meson-aiu.h>
15 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
16 model = "Hardkernel ODROID-C2";
24 stdout-path = "serial0:115200n8";
32 usb_otg_pwr: regulator-usb-pwrs {
33 compatible = "regulator-fixed";
[all …]
Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
/linux-6.12.1/drivers/gpu/drm/sun4i/
Dsun4i_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
15 #include <media/cec-pin.h>
37 #define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0)))
38 #define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16)
135 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1)
138 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1)
143 #define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1)
187 /* DDC CLK bit fields are the same, but the formula is not */
226 /* DDC FIFO register offset */
[all …]
Dsun4i_hdmi_i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
41 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
45 * For TX the threshold is for an empty FIFO. in fifo_transfer()
50 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
53 return -ETIMEDOUT; in fifo_transfer()
56 return -EIO; in fifo_transfer()
59 ioread8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
61 iowrite8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
64 regmap_field_force_write(hdmi->field_ddc_int_status, in fifo_transfer()
[all …]
/linux-6.12.1/drivers/gpu/drm/bridge/synopsys/
Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
20 #include <linux/dma-mapping.h>
23 #include <media/cec-notifier.h>
25 #include <uapi/linux/media-bus-format.h>
39 #include "dw-hdmi-audio.h"
40 #include "dw-hdmi-cec.h"
41 #include "dw-hdmi.h"
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/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm2835-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 interrupt-parent = <&intc>;
11 dma: dma-controller@7e007000 {
12 compatible = "brcm,bcm2835-dma";
25 /* dma channel 11-14 share one irq */
32 interrupt-names = "dma0",
47 "dma-shared-all";
48 #dma-cells = <1>;
49 brcm,dma-channel-mask = <0x7f35>;
52 intc: interrupt-controller@7e00b200 {
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/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6qdl-mba6.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
9 #include <dt-bindings/clock/imx6qdl-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/fsl-imx-audmux.h>
18 /delete-property/ mmc2;
19 /delete-property/ mmc3;
24 stdout-path = &uart2;
[all …]
Dimx6qdl-udoo.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
19 stdout-path = &uart2;
23 compatible = "gpio-backlight";
25 default-on;
29 gpio-poweroff {
30 compatible = "gpio-poweroff";
32 pinctrl-0 = <&pinctrl_power_off>;
33 pinctrl-names = "default";
43 * in reality it is a -20t (parallel) model,
[all …]
Dimx6qdl-var-dart.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Support for Variscite DART-MX6 Module
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/fsl-imx-audmux.h>
18 reg_3p3v: regulator-3p3v {
19 compatible = "regulator-fixed";
20 regulator-name = "3P3V";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
23 regulator-always-on;
[all …]
/linux-6.12.1/arch/arm/boot/dts/qcom/
Dqcom-apq8064-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 sdcc1_default_state: sdcc1-default-state {
5 clk-pins {
7 drive-strength = <16>;
8 bias-disable;
11 cmd-pins {
13 drive-strength = <10>;
14 bias-pull-up;
17 data-pins {
19 drive-strength = <10>;
[all …]
/linux-6.12.1/drivers/bluetooth/
Dhci_intel.c1 // SPDX-License-Identifier: GPL-2.0-or-later
109 struct intel_data *intel = hu->priv; in intel_wait_booting()
112 err = wait_on_bit_timeout(&intel->flags, STATE_BOOTING, in intel_wait_booting()
116 if (err == -EINTR) { in intel_wait_booting()
117 bt_dev_err(hu->hdev, "Device boot interrupted"); in intel_wait_booting()
118 return -EINTR; in intel_wait_booting()
122 bt_dev_err(hu->hdev, "Device boot timeout"); in intel_wait_booting()
123 return -ETIMEDOUT; in intel_wait_booting()
132 struct intel_data *intel = hu->priv; in intel_wait_lpm_transaction()
135 err = wait_on_bit_timeout(&intel->flags, STATE_LPM_TRANSACTION, in intel_wait_lpm_transaction()
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/ls/
Dls1021a-tqmls1021a-mbls1021a.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
5 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/leds/leds-pca9532.h>
15 #include <dt-bindings/net/ti-dp83867.h>
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