counts (full) in projects: linux-6.12.1

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/linux-6.12.1/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
D	other.json	3 "PublicDescription": "This event counts the occurrence count of the micro-operation split.", 6 "BriefDescription": "This event counts the occurrence count of the micro-operation split." 9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
D	pipeline.json	9 "PublicDescription": "This event counts valid cycles of EAGA pipeline.", 12 "BriefDescription": "This event counts valid cycles of EAGA pipeline." 15 "PublicDescription": "This event counts valid cycles of EAGB pipeline.", 18 "BriefDescription": "This event counts valid cycles of EAGB pipeline." 21 "PublicDescription": "This event counts valid cycles of EXA pipeline.", 24 "BriefDescription": "This event counts valid cycles of EXA pipeline." 27 "PublicDescription": "This event counts valid cycles of EXB pipeline.", 30 "BriefDescription": "This event counts valid cycles of EXB pipeline." 33 "PublicDescription": "This event counts valid cycles of FLA pipeline.", 36 "BriefDescription": "This event counts valid cycles of FLA pipeline." [all …]
D	cache.json	45 …"PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", 48 … "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." 51 …"PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", 54 … "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." 57 "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.", 60 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." 63 "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", 66 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch." 69 "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.", 72 "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle." [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
D	spec_operation.json	4 "PublicDescription": "Counts branches which are speculatively executed and mispredicted." 8 "PublicDescription": "Counts branches speculatively executed and were predicted right." 12 "PublicDescription": "Counts operations that have been speculatively executed." 16 …"PublicDescription": "Counts micro-operations speculatively executed. This is the count of the num… 20 …"PublicDescription": "Counts unaligned memory read operations issued by the CPU. This event counts… 24 …"PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event count… 28 …"PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unal… 32 …"PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: … 36 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … 40 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … [all …]
D	tlb.json	4 …Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in… 8 …Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …"PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses i… 20 …"PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and in… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 28 …"PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB dr… 32 …"PublicDescription": "Counts instruction memory translation table walks caused by a miss in the L2… 36 …Counts level 1 data TLB refills caused by memory read operations. If there are multiple misses in … 40 …Counts level 1 data TLB refills caused by data side memory write operations. If there are multiple… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
D	spec_operation.json	4 "PublicDescription": "Counts branches which are speculatively executed and mispredicted." 8 "PublicDescription": "Counts branches speculatively executed and were predicted right." 12 "PublicDescription": "Counts operations that have been speculatively executed." 16 …"PublicDescription": "Counts micro-operations speculatively executed. This is the count of the num… 20 …"PublicDescription": "Counts unaligned memory read operations issued by the CPU. This event counts… 24 …"PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event count… 28 …"PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unal… 32 …"PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: … 36 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … 40 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … [all …]
D	tlb.json	4 …Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in… 8 …Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …"PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses i… 20 …"PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and in… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 28 …"PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB dr… 32 …"PublicDescription": "Counts instruction memory translation table walks caused by a miss in the L2… 36 …Counts level 1 data TLB refills caused by memory read operations. If there are multiple misses in … 40 …Counts level 1 data TLB refills caused by data side memory write operations. If there are multiple… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/alderlaken/
D	cache.json	3 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 7 …Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests i… 12 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 16 …Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests in… 21 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o… 25 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache … 30 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o… 34 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache … 39 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o… 43 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache … [all …]
/linux-6.12.1/tools/perf/util/
D	counts.c	6 #include "counts.h" 12 struct perf_counts counts = zalloc(sizeof(counts)); in perf_counts__new() local 14 if (counts) { in perf_counts__new() 19 free(counts); in perf_counts__new() 23 counts->values = values; in perf_counts__new() 27 xyarray__delete(counts->values); in perf_counts__new() 28 free(counts); in perf_counts__new() 32 counts->loaded = values; in perf_counts__new() 35 return counts; in perf_counts__new() 38 void perf_counts__delete(struct perf_counts *counts) in perf_counts__delete() argument [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
D	spec_operation.json	4 "PublicDescription": "Counts branches which are speculatively executed and mispredicted." 8 "PublicDescription": "Counts branches speculatively executed and were predicted right." 12 "PublicDescription": "Counts operations that have been speculatively executed." 16 …"PublicDescription": "Counts unaligned memory read operations issued by the CPU. This event counts… 20 …"PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event count… 24 …"PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unal… 28 …"PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: … 32 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … 36 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and … 40 … "PublicDescription": "Counts store-exclusive operations that have been speculatively executed." [all …]
D	tlb.json	4 …Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in… 8 …Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …"PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses i… 20 …"PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and in… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 28 …"PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB dr… 32 …"PublicDescription": "Counts instruction memory translation table walks caused by a miss in the L2… 36 …Counts level 1 data TLB refills caused by memory read operations. If there are multiple misses in … 40 …Counts level 1 data TLB refills caused by data side memory write operations. If there are multiple… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
D	branch.json	18 …anch executed. This event counts when any branch that the conditional predictor can predict is ret… 21 …anch executed. This event counts when any branch that the conditional predictor can predict is ret… 24 …counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired… 27 …counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired… 30 …counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predict… 33 …counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predict… 36 …s event counts when any branch that the conditional predictor can predict is retired and has mispr… 39 …s event counts when any branch that the conditional predictor can predict is retired and has mispr… 42 …vent counts when any indirect branch that the BTAC can predict is retired, was taken, and correctl… 45 …vent counts when any indirect branch that the BTAC can predict is retired, was taken, and correctl… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/knightslanding/
D	pipeline.json	3 "BriefDescription": "Counts the number of branch instructions retired (Precise Event)", 11 … "BriefDescription": "Counts the number of near CALL branch instructions retired. (Precise Event)", 20 "BriefDescription": "Counts the number of far branch instructions retired. (Precise Event)", 29 …"BriefDescription": "Counts the number of near indirect CALL branch instructions retired. (Precise… 38 …"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps.… 47 …"BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL… 56 …"BriefDescription": "Counts the number of near relative CALL branch instructions retired. (Precise… 65 … "BriefDescription": "Counts the number of near RET branch instructions retired. (Precise Event)", 74 …"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps … 83 …"BriefDescription": "Counts the number of mispredicted branch instructions retired (Precise Event)… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/grandridge/
D	cache.json	3 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 7 …Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests i… 12 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 16 …Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests in… 21 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instr… 29 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o… 33 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache … 38 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icach… 46 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icach… 54 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 de… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/sierraforest/
D	cache.json	3 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 7 …Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests i… 12 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 16 …Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests in… 21 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instr… 29 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o… 33 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache … 38 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icach… 46 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icach… 54 …"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 de… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/elkhartlake/
D	pipeline.json	3 …"BriefDescription": "Counts the total number of branch instructions retired for all branch types.", 8 …"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP… 12 "BriefDescription": "Counts the number of near CALL branch instructions retired.", 21 …"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far … 30 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", 39 …"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructio… 48 …"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instruct… 57 "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", 66 "BriefDescription": "Counts the number of near RET branch instructions retired.", 75 …"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions… [all …]
D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 11 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 23 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag… 32 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 37 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 41 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 46 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 50 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… [all …]
D	cache.json	3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th… 7 …Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due … 11 …"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, s… 15 …"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, … 20 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue… 24 …"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queu… 28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 32 …: "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door reques… 36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 40 …ion": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request onl… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/snowridgex/
D	pipeline.json	3 …"BriefDescription": "Counts the total number of branch instructions retired for all branch types.", 8 …"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP… 12 "BriefDescription": "Counts the number of near CALL branch instructions retired.", 21 …"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far … 30 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", 39 …"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructio… 48 …"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instruct… 57 "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", 66 "BriefDescription": "Counts the number of near RET branch instructions retired.", 75 …"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions… [all …]
D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 11 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 23 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag… 32 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 37 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 41 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 46 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 50 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… [all …]
D	cache.json	3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th… 7 …Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due … 11 …"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, s… 15 …"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, … 20 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue… 24 …"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queu… 28 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 32 …: "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door reques… 36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 40 …ion": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request onl… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
D	branch.json	18 … executed.This event counts when any branch which can be predicted by the conditional predictor is… 21 … executed.This event counts when any branch which can be predicted by the conditional predictor is… 24 …counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicte… 27 …counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicte… 30 …counts when any indirect branch which can be predicted by the BTAC is retired, was taken and corre… 33 …counts when any indirect branch which can be predicted by the BTAC is retired, was taken and corre… 36 …nt counts when any branch which can be predicted by the conditional predictor is retired, and has … 39 …nt counts when any branch which can be predicted by the conditional predictor is retired, and has … 42 … counts when any indirect branch which can be predicted by the BTAC is retired, was taken and corr… 45 … counts when any indirect branch which can be predicted by the BTAC is retired, was taken and corr… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwell/
D	cache.json	7 …"PublicDescription": "This event counts L1D data line replacements including opportunistic replace… 25 …"PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle numbe… 35 "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", 54 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 63 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does… 72 …"PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state fillin… 81 …"PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filli… 90 …"PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling t… 107 "PublicDescription": "This event counts the total number of L2 code requests.", 116 …"PublicDescription": "This event counts the number of demand Data Read requests (including request… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	7 …Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly… 15 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache … 24 …"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That … 33 …"PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects… 41 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 50 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line… 61 …"PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM. Even… 72 …"PublicDescription": "Counts load uops retired where the cache line containing the data was in the… 83 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 94 "PublicDescription": "Counts load uops retired that miss the L1 data cache.", [all …]
/linux-6.12.1/tools/lib/perf/tests/
D	test-evsel.c	40 struct perf_counts_values counts = { .val = 0 }; in test_stat_cpu() local 42 perf_evsel__read(evsel, idx, 0, &counts); in test_stat_cpu() 43 __T("failed to read value for evsel", counts.val != 0); in test_stat_cpu() 55 struct perf_counts_values counts = { .val = 0 }; in test_stat_thread() local 75 perf_evsel__read(evsel, 0, 0, &counts); in test_stat_thread() 76 __T("failed to read value for evsel", counts.val != 0); in test_stat_thread() 87 struct perf_counts_values counts = { .val = 0 }; in test_stat_thread_enable() local 108 perf_evsel__read(evsel, 0, 0, &counts); in test_stat_thread_enable() 109 __T("failed to read value for evsel", counts.val == 0); in test_stat_thread_enable() 114 perf_evsel__read(evsel, 0, 0, &counts); in test_stat_thread_enable() [all …]

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