x86/elkhartlake/cache.json

3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th…
7 …Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due …
11 …"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, s…
15 …"PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, …
20 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue…
24 …"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queu…
28 …   "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
32 …: "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects  front door reques…
36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe…
40 …ion": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request onl…
45 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p…
49 …on": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request onl…
54 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou…
58 …"Counts the number of L2 Cache accesses that miss the L2 and get BBL reject  short and long reject…
63 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o…
67 …Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests i…
72 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on…
76 …Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests in…
81 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o…
85 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache …
90 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o…
94 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache …
99 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o…
103 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache …
108 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o…
112 …"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache …
117 …"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss whi…
125 …"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss whi…
133 …"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hi…
141 …"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hi…
145 …"PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which h…
150 …"BriefDescription": "Counts the number of cycles the core is stalled due to a store buffer being f…
158         "BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
168 …"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a s…
178         "BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.",
188 …      "BriefDescription": "Counts the number of load uops retired that miss in the L1 data cache.",
198         "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
208         "BriefDescription": "Counts the number of load uops retired that miss in the L2 cache.",
218         "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
228         "BriefDescription": "Counts the number of memory uops retired.",
234 …"PublicDescription": "Counts the number of memory uops retired.  A single uop that performs both a…
239         "BriefDescription": "Counts the number of load uops retired.",
245         "PublicDescription": "Counts the total number of load uops retired.",
250         "BriefDescription": "Counts the number of store uops retired.",
256         "PublicDescription": "Counts the total number of store uops retired.",
261 …    "BriefDescription": "Counts the number of load uops retired that performed one or more locks.",
271         "BriefDescription": "Counts the number of memory uops retired that were splits.",
281         "BriefDescription": "Counts the number of retired split load uops.",
291         "BriefDescription": "Counts the number of retired split store uops.",
301         "BriefDescription": "Counts all code reads that were supplied by the L3 cache.",
311 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
321 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
331 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
341 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
351 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was n…
361 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by t…
371 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we…
381 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we…
391 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we…
401 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we…
411 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we…
421 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we…
431 …"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and sof…
441 …"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and sof…
451 …"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and sof…
461 …"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and sof…
471 …"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and sof…
481 …"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and sof…
557 …"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive…
567 …"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive…
577 …"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive…
587 …"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive…
597 …"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive…
607 …"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive…
617 …"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were suppl…
627 …"BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREF…
637 …"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) t…
647 …"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) t…
657 …"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) t…
667 …"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) t…
677 …"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) t…
687 …"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) t…
697 …"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) t…
707 …"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) t…
717 …"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) t…
727 …"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) t…
737 …"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) t…
747 …"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) t…
757 …"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that we…
767 …"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that we…
777 …"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that we…
787 …"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that we…
797 …"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that we…
807 …"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that we…
817 …"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were sup…
827 …"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were sup…
837 …"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that we…
847 …"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefet…
857 …"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefet…
867 …"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefet…
877 …"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefet…
887 …"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefet…
897 …"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefet…
907         "BriefDescription": "Counts streaming stores that were supplied by the L3 cache.",
917         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.",
927 …"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop…
937 …"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop…
947 …"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop…
957 …"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop…
967 …"BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoo…
977         "BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.",
987 …"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the f…