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/linux-6.12.1/drivers/hwtracing/coresight/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for CoreSight drivers.
7 subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
8 subdir-ccflags-y += -Wmissing-declarations
9 subdir-ccflags-y += -Wmissing-format-attribute
10 subdir-ccflags-y += -Wmissing-prototypes
11 subdir-ccflags-y += -Wold-style-definition
12 subdir-ccflags-y += -Wmissing-include-dirs
13 subdir-ccflags-y += -Wno-sign-compare
15 $(call cc-option, -Wrestrict) \
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
13 This framework provides a kernel interface for the CoreSight debug
15 a topological view of the CoreSight components based on a DT
20 module will be called coresight.
22 if CORESIGHT
24 tristate "CoreSight Link and Sink drivers"
26 This enables support for CoreSight link and sink drivers that are
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Dcoresight-etm3x-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
5 * Description: CoreSight Program Flow Trace driver
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
33 #include "coresight-etm.h"
34 #include "coresight-etm-perf.h"
35 #include "coresight-trace-id.h"
57 drvdata->os_unlock = true; in etm_os_unlock()
89 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR); in etm_set_pwrup()
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/linux-6.12.1/arch/arm/boot/dts/hisilicon/
Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/linux-6.12.1/Documentation/devicetree/bindings/arm/
Darm,coresight-etm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Embedded Trace MacroCell
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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/linux-6.12.1/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/linux-6.12.1/arch/arm/boot/dts/xilinx/
Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/linux-6.12.1/drivers/pmdomain/renesas/
Drmobile-sysc.c1 // SPDX-License-Identifier: GPL-2.0
9 * based on pm-sh7372.c
49 unsigned int mask = BIT(rmobile_pd->bit_shift); in rmobile_pd_power_down()
52 if (rmobile_pd->suspend) { in rmobile_pd_power_down()
53 int ret = rmobile_pd->suspend(); in rmobile_pd_power_down()
59 if (readl(rmobile_pd->base + PSTR) & mask) { in rmobile_pd_power_down()
60 writel(mask, rmobile_pd->base + SPDCR); in rmobile_pd_power_down()
62 readl_poll_timeout_atomic(rmobile_pd->base + SPDCR, val, in rmobile_pd_power_down()
66 pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", genpd->name, mask, in rmobile_pd_power_down()
67 readl(rmobile_pd->base + PSTR)); in rmobile_pd_power_down()
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/linux-6.12.1/arch/arm/boot/dts/qcom/
Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Domap3-beagle-xm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap3";
15 cpu0-supply = <&vcc>;
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-frequency = <26000000>;
37 led-controller-1 {
38 compatible = "gpio-leds";
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Domap3-beagle.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
15 cpu0-supply = <&vcc>;
30 compatible = "gpio-leds";
31 led-pmu-stat {
36 led-heartbeat {
38 gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
39 linux,default-trigger = "heartbeat";
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/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx7d.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
20 #cooling-cells = <2>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
26 compatible = "arm,cortex-a7";
29 clock-frequency = <996000000>;
30 operating-points-v2 = <&cpu0_opp_table>;
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Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux-6.12.1/Documentation/trace/coresight/
Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
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/linux-6.12.1/arch/arm/boot/dts/st/
Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/ste-db8500-clkout.h>
9 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
10 #include <dt-bindings/mfd/dbx500-prcmu.h>
11 #include <dt-bindings/arm/ux500_pm_domains.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/thermal/thermal.h>
16 #address-cells = <1>;
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/linux-6.12.1/arch/arm/boot/dts/microchip/
Dsama5d2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
13 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 interrupt-parent = <&aic>;
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/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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Dr8a73a4.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/r8a73a4-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a15";
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