Searched +full:cn10k +full:- +full:tad +full:- +full:pmu (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Marvell CN10K LLC-TAD performance monitor10 - Bhaskara Budiredla <bbudiredla@marvell.com>13 The Tag-and-Data units (TADs) maintain coherence and contain CN10K14 shared on-chip last level cache (LLC). The tad pmu measures the15 performance of last-level cache. Each tad pmu supports up to eight18 The DT setup comprises of number of tad blocks, the sizes of pmu[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Marvell CN10K LLC-TAD perf driver24 #define to_tad_pmu(p) (container_of(p, struct tad_pmu, pmu))31 struct pmu pmu; member44 struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu); in tad_pmu_event_counter_read()45 struct hw_perf_event *hwc = &event->hw; in tad_pmu_event_counter_read()46 u32 counter_idx = hwc->idx; in tad_pmu_event_counter_read()51 prev = local64_read(&hwc->prev_count); in tad_pmu_event_counter_read()52 for (i = 0, new = 0; i < tad_pmu->region_cnt; i++) in tad_pmu_event_counter_read()53 new += readq(tad_pmu->regions[i].base + in tad_pmu_event_counter_read()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only10 tristate "ARM CCI PMU driver"14 Support for PMU events monitoring on the ARM CCI (Cache Coherent17 If compiled as a module, it will be called arm-cci.20 bool "support CCI-400"25 CCI-400 provides 4 independent event counters counting events related29 bool "support CCI-500/CCI-550"33 CCI-500/CCI-550 both provide 8 independent event counters, which can41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)45 tristate "Arm CMN-600 PMU support"[all …]