bindings/perf/marvell-cn10k-tad.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN10K LLC-TAD performance monitor
10   - Bhaskara Budiredla <bbudiredla@marvell.com>
13   The Tag-and-Data units (TADs) maintain coherence and contain CN10K
14   shared on-chip last level cache (LLC). The tad pmu measures the
15   performance of last-level cache. Each tad pmu supports up to eight
18   The DT setup comprises of number of tad blocks, the sizes of pmu
19   regions, tad blocks and overall base address of the HW.
23     const: marvell,cn10k-tad-pmu
28   marvell,tad-cnt:
32   marvell,tad-page-size:
33     description: specifies the size of each tad page
36   marvell,tad-pmu-page-size:
37     description: specifies the size of page that the pmu uses
41   - compatible
42   - reg
43   - marvell,tad-cnt
44   - marvell,tad-page-size
45   - marvell,tad-pmu-page-size
50   - |
52     tad {
53         #address-cells = <2>;
54         #size-cells = <2>;
57             compatible = "marvell,cn10k-tad-pmu";
59             marvell,tad-cnt = <1>;
60             marvell,tad-page-size = <0x1000>;
61             marvell,tad-pmu-page-size = <0x1000>;