| /linux-6.12.1/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
22 struct iproc_asiu_div div; member
38 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_enable() local
39 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable()
43 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
46 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
47 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
48 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
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| /linux-6.12.1/drivers/clk/meson/ |
| D | clk-regmap.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include "clk-regmap.h"
12 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_endisable() local
13 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_endisable()
14 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_regmap_gate_endisable()
18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
34 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_is_enabled() local
35 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_is_enabled()
38 regmap_read(clk->map, gate->offset, &val); in clk_regmap_gate_is_enabled()
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| D | clk-cpu-dyndiv.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-cpu-dyndiv.h"
14 meson_clk_cpu_dyndiv_data(struct clk_regmap *clk) in meson_clk_cpu_dyndiv_data() argument
16 return (struct meson_clk_cpu_dyndiv_data *)clk->data; in meson_clk_cpu_dyndiv_data()
22 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_recalc_rate() local
23 struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); in meson_clk_cpu_dyndiv_recalc_rate()
26 meson_parm_read(clk->map, &data->div), in meson_clk_cpu_dyndiv_recalc_rate()
27 NULL, 0, data->div.width); in meson_clk_cpu_dyndiv_recalc_rate()
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| D | sclk-div.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 * hi = [0 - val]
19 #include <linux/clk-provider.h>
22 #include "clk-regmap.h"
23 #include "sclk-div.h"
26 meson_sclk_div_data(struct clk_regmap *clk) in meson_sclk_div_data() argument
28 return (struct meson_sclk_div_data *)clk->data; in meson_sclk_div_data()
33 return (1 << sclk->div.width) - 1; in sclk_div_maxval()
44 int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate); in sclk_div_getdiv() local
46 return clamp(div, 2, maxdiv); in sclk_div_getdiv()
[all …]
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| /linux-6.12.1/arch/mips/boot/dts/mobileye/ |
| D | eyeq5-clocks.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
6 #include <dt-bindings/clock/mobileye,eyeq5-clk.h>
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <30000000>;
17 occ_cpu: occ-cpu {
18 compatible = "fixed-factor-clock";
20 #clock-cells = <0>;
21 clock-div = <1>;
22 clock-mult = <1>;
[all …]
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| /linux-6.12.1/drivers/clk/spear/ |
| D | spear1340_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-spear13xx/spear1340_clock.c
12 #include <linux/clk/spear.h>
16 #include "clk.h"
175 /* vco-pll4 rate configuration table, in ascending order of rates */
188 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
189 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
190 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
191 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
192 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
[all …]
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| D | clk-frac-synth.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt) "clk-frac-synth: " fmt
11 #include <linux/clk-provider.h>
15 #include "clk.h"
24 * Fout= Fin/2*div (division factor)
25 * div is 17 bits:-
26 * 0-13 (fractional part)
27 * 14-16 (integer part)
28 * div is (16-14 bits).(13-0 bits) (in binary)
30 * Fout = Fin/(2 * div)
[all …]
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| /linux-6.12.1/drivers/clk/mxs/ |
| D | clk-div.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
9 #include "clk.h"
12 * struct clk_div - mxs integer divider clock
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
[all …]
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| D | clk-frac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
10 #include "clk.h"
13 * struct clk_frac - mxs fractional divider clock
37 u32 div; in clk_frac_recalc_rate() local
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
43 tmp_rate = (u64)parent_rate * div; in clk_frac_recalc_rate()
44 return tmp_rate >> frac->width; in clk_frac_recalc_rate()
52 u32 div; in clk_frac_round_rate() local
[all …]
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| /linux-6.12.1/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
[all …]
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| D | clk-sun9i-cpus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
33 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
34 (div << SUN9I_CPUS_DIV_SHIFT))
39 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
40 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
57 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
[all …]
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| D | clk-sun8i-mbus.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
28 const char *clk_name = node->name; in sun8i_a23_mbus_setup()
30 struct clk_divider *div; in sun8i_a23_mbus_setup() local
33 struct clk *clk; in sun8i_a23_mbus_setup() local
43 pr_err("Could not get registers for sun8i-mbus-clk\n"); in sun8i_a23_mbus_setup()
47 div = kzalloc(sizeof(*div), GFP_KERNEL); in sun8i_a23_mbus_setup()
[all …]
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| D | clk-sun6i-ar100.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
11 #include <linux/clk-provider.h>
17 #include "clk-factors.h"
20 * sun6i_get_ar100_factors - Calculates factors p, m for AR100
27 unsigned long div; in sun6i_get_ar100_factors() local
31 if (req->rate > req->parent_rate) in sun6i_get_ar100_factors()
32 req->rate = req->parent_rate; in sun6i_get_ar100_factors()
34 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_get_ar100_factors()
36 if (div < 32) in sun6i_get_ar100_factors()
[all …]
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
12 #include "clk.h"
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
29 if (div < 0) in get_div()
[all …]
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| D | clk-tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on drivers/clk/tegra/clk-emc.c
7 * Copyright (C) 2019 GRATE-DRIVER project
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
13 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
21 #include "clk.h"
58 u32 val, div; in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
61 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_recalc_rate()
[all …]
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| D | clk-sdmmc-mux.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * based on clk-mux.c
9 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
13 #include <linux/clk-provider.h>
18 #include "clk.h"
50 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_get_parent()
73 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_set_parent()
82 writel(val, sdmmc_mux->reg); in clk_sdmmc_mux_set_parent()
92 int div; in clk_sdmmc_mux_recalc_rate() local
95 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_recalc_rate()
[all …]
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| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * samsung/clk.c
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
25 #include "../clk-fractional-divider.h"
26 #include "clk.h"
32 * src1 --|--\
33 * |M |--[GATE]-[DIV]-
34 * src2 --|--/
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| /linux-6.12.1/drivers/clk/ |
| D | clk-fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
[all …]
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| D | clk-qoriq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
33 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
39 struct clk *clk; member
44 struct clockgen_pll_div div[MAX_PLL_DIV]; member
53 int div; /* PLL_DIVn */ member
82 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
91 struct clk *sysclk, *coreclk;
[all …]
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| /linux-6.12.1/drivers/clk/starfive/ |
| D | clk-starfive-jh71x0.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
8 #include <linux/clk-provider.h>
13 #include "clk-starfive-jh71x0.h"
20 static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk) in jh71x0_priv_from() argument
22 return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]); in jh71x0_priv_from()
25 static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk) in jh71x0_clk_reg_get() argument
27 struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); in jh71x0_clk_reg_get()
28 void __iomem *reg = priv->base + 4 * clk->idx; in jh71x0_clk_reg_get()
33 static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value) in jh71x0_clk_reg_rmw() argument
[all …]
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| /linux-6.12.1/drivers/clk/renesas/ |
| D | rcar-gen2-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
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| D | rcar-gen3-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
[all …]
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| /linux-6.12.1/drivers/clk/hisilicon/ |
| D | clkdivider-hi6220.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
17 #include "clk.h"
19 #define div_mask(width) ((1 << (width)) - 1)
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
29 * @table: the div table that the divider supports
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
[all …]
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| /linux-6.12.1/drivers/clk/pistachio/ |
| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
13 #include "clk.h"
24 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); in pistachio_clk_alloc_provider()
25 if (!p->clk_data.clks) in pistachio_clk_alloc_provider()
27 p->clk_data.clk_num = num_clks; in pistachio_clk_alloc_provider()
28 p->node = node; in pistachio_clk_alloc_provider()
29 p->base = of_iomap(node, 0); in pistachio_clk_alloc_provider()
30 if (!p->base) { in pistachio_clk_alloc_provider()
[all …]
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| /linux-6.12.1/drivers/clk/microchip/ |
| D | clk-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include <asm/mach-pic32/pic32.h>
15 #include "clk-core.h"
78 /* add instruction pipeline delay while CPU clock is in-transition. */
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
125 unsigned long div, div_up; in calc_best_divided_rate() local
131 div = parent_rate / rate; in calc_best_divided_rate()
[all …]
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