1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
8 #include <linux/clk-provider.h>
13 #include "clk-starfive-jh71x0.h"
20 static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)  in jh71x0_priv_from()  argument
22 	return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);  in jh71x0_priv_from()
25 static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)  in jh71x0_clk_reg_get()  argument
27 	struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);  in jh71x0_clk_reg_get()
28 	void __iomem *reg = priv->base + 4 * clk->idx;  in jh71x0_clk_reg_get()
33 static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)  in jh71x0_clk_reg_rmw()  argument
35 	struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);  in jh71x0_clk_reg_rmw()
36 	void __iomem *reg = priv->base + 4 * clk->idx;  in jh71x0_clk_reg_rmw()
39 	spin_lock_irqsave(&priv->rmw_lock, flags);  in jh71x0_clk_reg_rmw()
42 	spin_unlock_irqrestore(&priv->rmw_lock, flags);  in jh71x0_clk_reg_rmw()
47 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_enable()  local
49 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);  in jh71x0_clk_enable()
55 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_disable()  local
57 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);  in jh71x0_clk_disable()
62 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_is_enabled()  local
64 	return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);  in jh71x0_clk_is_enabled()
70 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_recalc_rate()  local
71 	u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;  in jh71x0_clk_recalc_rate()  local
73 	return div ? parent_rate / div : 0;  in jh71x0_clk_recalc_rate()
79 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_determine_rate()  local
80 	unsigned long parent = req->best_parent_rate;  in jh71x0_clk_determine_rate()
81 	unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);  in jh71x0_clk_determine_rate()
82 	unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);  in jh71x0_clk_determine_rate()  local
83 	unsigned long result = parent / div;  in jh71x0_clk_determine_rate()
87 	 * case 1: div hits the max divider value, which means it's less than  in jh71x0_clk_determine_rate()
91 	 * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is  in jh71x0_clk_determine_rate()
94 	 *   div - 1 = ceil(parent / rate) - 1 < parent / rate  in jh71x0_clk_determine_rate()
96 	 *   min_rate <= rate < parent / (div - 1)  in jh71x0_clk_determine_rate()
98 	if (result < req->min_rate && div > 1)  in jh71x0_clk_determine_rate()
99 		result = parent / (div - 1);  in jh71x0_clk_determine_rate()
101 	req->rate = result;  in jh71x0_clk_determine_rate()
109 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_set_rate()  local
110 	unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),  in jh71x0_clk_set_rate()  local
111 				  1UL, (unsigned long)clk->max_div);  in jh71x0_clk_set_rate()
113 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);  in jh71x0_clk_set_rate()
120 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_frac_recalc_rate()  local
121 	u32 reg = jh71x0_clk_reg_get(clk);  in jh71x0_clk_frac_recalc_rate()
131 	unsigned long parent100 = 100 * req->best_parent_rate;  in jh71x0_clk_frac_determine_rate()
132 	unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);  in jh71x0_clk_frac_determine_rate()
138 	if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)  in jh71x0_clk_frac_determine_rate()
140 	if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)  in jh71x0_clk_frac_determine_rate()
141 		result = parent100 / (div100 - 1);  in jh71x0_clk_frac_determine_rate()
143 	req->rate = result;  in jh71x0_clk_frac_determine_rate()
151 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_frac_set_rate()  local
156 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);  in jh71x0_clk_frac_set_rate()
162 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_get_parent()  local
163 	u32 value = jh71x0_clk_reg_get(clk);  in jh71x0_clk_get_parent()
170 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_set_parent()  local
173 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);  in jh71x0_clk_set_parent()
179 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_get_phase()  local
180 	u32 value = jh71x0_clk_reg_get(clk);  in jh71x0_clk_get_phase()
187 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_set_phase()  local
195 		return -EINVAL;  in jh71x0_clk_set_phase()
197 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);  in jh71x0_clk_set_phase()
208 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);  in jh71x0_clk_debug_init()  local
209 	struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);  in jh71x0_clk_debug_init()
212 	regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);  in jh71x0_clk_debug_init()
216 	regset->regs = &jh71x0_clk_reg;  in jh71x0_clk_debug_init()
217 	regset->nregs = 1;  in jh71x0_clk_debug_init()
218 	regset->base = priv->base + 4 * clk->idx;  in jh71x0_clk_debug_init()