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/linux-6.12.1/drivers/gpio/
Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
26 #include "gpiolib-of.h"
29 * This is Linux-specific flags. By default controllers' and Linux' mapping
31 * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
44 * of_gpio_named_count() - Count GPIOs for a device
53 * * %-EINVAL for an incorrectly formed "gpios" property, or
54 * * %-ENOENT for a missing "gpios" property.
69 return of_count_phandle_with_args(np, propname, "#gpio-cells"); in of_gpio_named_count()
73 * of_gpio_spi_cs_get_count() - special GPIO counting for SPI
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Dgpio-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * The GPIO chips are shared with pinctrl-nomadik if used; it needs access for
10 * This driver also handles the mobileye,eyeq5-gpio compatible. It is an STA2X11
14 * pinctrl-nomadik.
19 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
30 #include <linux/reset.h>
35 #include <linux/gpio/gpio-nomadik.h>
47 if (WARN_ON(nmk_chip->is_mobileye_soc)) in __nmk_gpio_set_slpm()
50 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); in __nmk_gpio_set_slpm()
55 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); in __nmk_gpio_set_slpm()
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Dgpio-xra1403.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for EXAR XRA1403 16-bit GPIO expander
23 #define XRA_PUR 0x08 /* Input Internal Pull-up Resistor Enable/Disable */
25 #define XRA_TSCR 0x0C /* Output Three-State Control */
33 struct gpio_chip chip; member
50 static int xra1403_direction_input(struct gpio_chip *chip, unsigned int offset) in xra1403_direction_input() argument
52 struct xra1403 *xra = gpiochip_get_data(chip); in xra1403_direction_input()
54 return regmap_update_bits(xra->regmap, to_reg(XRA_GCR, offset), in xra1403_direction_input()
58 static int xra1403_direction_output(struct gpio_chip *chip, unsigned int offset, in xra1403_direction_output() argument
62 struct xra1403 *xra = gpiochip_get_data(chip); in xra1403_direction_output()
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/linux-6.12.1/drivers/platform/mellanox/
Dmlxbf-bootctl.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * Request that the on-chip watchdog be enabled, or disabled, after
11 * the next chip soft reset. This call does not affect the current
12 * status of the on-chip watchdog. If non-zero, the argument
14 * will not be enabled after the next soft reset. Non-zero errors are
20 * Query the status which has been requested for the on-chip watchdog
21 * after the next chip soft reset. Returns the interval as set by
28 * reset. By default, the boot action is set by external chip pins,
29 * which are sampled on hard reset. Note that the boot action
33 * values. Non-zero errors are returned as documented below.
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/linux-6.12.1/sound/pcmcia/vx/
Dvxp_ops.c1 // SPDX-License-Identifier: GPL-2.0-or-later
40 struct snd_vxpocket *chip = to_vxpocket(_chip); in vxp_reg_addr() local
41 return chip->port + vxp_reg_offset[reg]; in vxp_reg_addr()
45 * snd_vx_inb - read a byte from the register
48 static unsigned char vxp_inb(struct vx_core *chip, int offset) in vxp_inb() argument
50 return inb(vxp_reg_addr(chip, offset)); in vxp_inb()
54 * snd_vx_outb - write a byte on the register
58 static void vxp_outb(struct vx_core *chip, int offset, unsigned char val) in vxp_outb() argument
60 outb(val, vxp_reg_addr(chip, offset)); in vxp_outb()
67 #define vx_inb(chip,reg) vxp_inb((struct vx_core *)(chip), VX_##reg) argument
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/linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dchip.c1 // SPDX-License-Identifier: ISC
18 #include "chip.h"
20 /* SOC Interconnect types (aka chip types) */
24 /* PL-368 DMP definitions */
84 /* chip core base & ramsize */
223 struct brcmf_chip_priv *chip; member
236 u32 reset);
237 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
246 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh)); in brcmf_chip_sb_corerev()
247 core->rev = SBCOREREV(regdata); in brcmf_chip_sb_corerev()
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Dchip.h1 // SPDX-License-Identifier: ISC
14 * struct brcmf_chip - chip level information.
16 * @chip: chip identifier.
17 * @chiprev: chip revision.
24 * @ramsize: amount of RAM on chip including retention.
25 * @srsize: amount of retention RAM on chip.
26 * @name: string representation of the chip identifier.
29 u32 chip; member
43 * struct brcmf_core - core related information.
56 * struct brcmf_buscore_ops - buscore specific callbacks.
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/linux-6.12.1/drivers/media/tuners/
Dtua9001.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * struct tua9001_platform_data - Platform data for the tua9001 driver
29 * CEN - chip enable
30 * 0 = chip disabled (chip off)
31 * 1 = chip enabled (chip on)
33 * RESETN - chip reset
34 * 0 = reset disabled (chip reset off)
35 * 1 = reset enabled (chip reset on)
37 * RXEN - RX enable
38 * 0 = RX disabled (chip idle)
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/linux-6.12.1/Documentation/devicetree/bindings/power/reset/
Docelot-reset.txt1 Microsemi Ocelot reset controller
3 The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
6 The reset registers are both present in the MSCC vcoreiii MIPS and
11 - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
12 "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
15 reset@1070008 {
16 compatible = "mscc,ocelot-chip-reset";
/linux-6.12.1/sound/soc/
Dsoc-ac97.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-ac97.c -- ALSA SoC Audio Layer AC97 support
11 // with code, comments and ideas from :-
52 static inline struct snd_soc_component *gpio_to_component(struct gpio_chip *chip) in gpio_to_component() argument
54 struct snd_ac97_gpio_priv *gpio_priv = gpiochip_get_data(chip); in gpio_to_component()
56 return gpio_priv->component; in gpio_to_component()
59 static int snd_soc_ac97_gpio_request(struct gpio_chip *chip, unsigned int offset) in snd_soc_ac97_gpio_request() argument
62 return -EINVAL; in snd_soc_ac97_gpio_request()
67 static int snd_soc_ac97_gpio_direction_in(struct gpio_chip *chip, in snd_soc_ac97_gpio_direction_in() argument
70 struct snd_soc_component *component = gpio_to_component(chip); in snd_soc_ac97_gpio_direction_in()
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/linux-6.12.1/sound/isa/sb/
Dsb8_midi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Routines for control of SoundBlaster cards - MIDI interface
6 * --
22 irqreturn_t snd_sb8dsp_midi_interrupt(struct snd_sb *chip) in snd_sb8dsp_midi_interrupt() argument
28 if (!chip) in snd_sb8dsp_midi_interrupt()
31 rmidi = chip->rmidi; in snd_sb8dsp_midi_interrupt()
33 inb(SBP(chip, DATA_AVAIL)); /* ack interrupt */ in snd_sb8dsp_midi_interrupt()
37 spin_lock(&chip->midi_input_lock); in snd_sb8dsp_midi_interrupt()
38 while (max-- > 0) { in snd_sb8dsp_midi_interrupt()
39 if (inb(SBP(chip, DATA_AVAIL)) & 0x80) { in snd_sb8dsp_midi_interrupt()
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/linux-6.12.1/Documentation/devicetree/bindings/reset/
Dmarvell,berlin2-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell Berlin reset controller
11 - Antoine Tenart <atenart@kernel.org>
13 description: The reset controller node must be a sub-node of the chip
18 const: marvell,berlin2-reset
20 "#reset-cells":
24 - compatible
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/linux-6.12.1/sound/i2c/other/
Dak4xxx-adda.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2000-2004 Jaroslav Kysela <perex@perex.cz>,
18 #include <sound/ak4xxx-adda.h>
26 void snd_akm4xxx_write(struct snd_akm4xxx *ak, int chip, unsigned char reg, in snd_akm4xxx_write() argument
29 ak->ops.lock(ak, chip); in snd_akm4xxx_write()
30 ak->ops.write(ak, chip, reg, val); in snd_akm4xxx_write()
33 snd_akm4xxx_set(ak, chip, reg, val); in snd_akm4xxx_write()
34 ak->ops.unlock(ak, chip); in snd_akm4xxx_write()
39 /* reset procedure for AK4524 and AK4528 */
42 unsigned int chip; in ak4524_reset() local
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/linux-6.12.1/sound/soc/sof/intel/
Dhda-dsp.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
21 #include <sound/hda-mlink.h>
24 #include "../sof-audio.h"
28 #include "hda-ipc.h"
47 const struct sof_intel_dsp_desc *chip; in hda_get_interfaces() local
49 chip = get_chip_info(sdev->pdata); in hda_get_interfaces()
50 switch (chip->hw_ip_version) { in hda_get_interfaces()
91 return interface_mask[sdev->dspless_mode_selected]; in hda_get_interface_mask()
98 const struct sof_intel_dsp_desc *chip; in hda_is_chain_dma_supported() local
100 if (sdev->dspless_mode_selected) in hda_is_chain_dma_supported()
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/linux-6.12.1/drivers/net/dsa/
Dlan9303-core.c1 // SPDX-License-Identifier: GPL-2.0-only
195 /* the built-in PHYs are of type LAN911X */
211 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
248 * tries to detect and read an external EEPROM after reset and acts as in lan9303_read()
256 if (ret != -EAGAIN) in lan9303_read()
261 return -EIO; in lan9303_read()
264 static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask) in lan9303_read_wait() argument
272 ret = lan9303_read(chip->regmap, offset, &reg); in lan9303_read_wait()
274 dev_err(chip->dev, "%s failed to read offset %d: %d\n", in lan9303_read_wait()
283 return -ETIMEDOUT; in lan9303_read_wait()
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/linux-6.12.1/drivers/net/dsa/mv88e6xxx/
Dchip.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
28 /* PVT limits for 4-bit port and 5-bit switch */
110 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
149 * ports 2-4 are not routet to pins.
152 /* Multi-chip Addressing Mode.
154 * when it is non-zero, and use indirect access to internal registers.
157 /* Dual-chip Addressing Mode
213 struct irq_chip chip; member
277 struct mv88e6xxx_chip *chip; member
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Dglobal1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
13 #include "chip.h"
16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) in mv88e6xxx_g1_read() argument
18 int addr = chip->info->global1_addr; in mv88e6xxx_g1_read()
20 return mv88e6xxx_read(chip, addr, reg, val); in mv88e6xxx_g1_read()
23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) in mv88e6xxx_g1_write() argument
25 int addr = chip->info->global1_addr; in mv88e6xxx_g1_write()
27 return mv88e6xxx_write(chip, addr, reg, val); in mv88e6xxx_g1_write()
30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int in mv88e6xxx_g1_wait_bit() argument
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Dchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88e6xxx Ethernet switch single-chip support
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
35 #include "chip.h"
46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) in assert_reg_lock() argument
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { in assert_reg_lock()
49 dev_err(chip->dev, "Switch registers lock not held!\n"); in assert_reg_lock()
54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) in mv88e6xxx_read() argument
58 assert_reg_lock(chip); in mv88e6xxx_read()
60 err = mv88e6xxx_smi_read(chip, addr, reg, val); in mv88e6xxx_read()
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/linux-6.12.1/Documentation/devicetree/bindings/net/nfc/
Dmarvell,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - marvell,nfc-i2c
16 - marvell,nfc-spi
17 - marvell,nfc-uart
19 hci-muxed:
22 Specifies that the chip is muxing NCI over HCI frames
30 reset-n-io:
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/linux-6.12.1/sound/pci/
Dintel8x0m.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
29 static int index = -2; /* Exclude the first card */
38 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
53 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
54 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
55 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
56 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
57 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
58 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
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/linux-6.12.1/drivers/hwmon/
Daspeed-g6-pwm-tach.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Q := (DIV_L + 1) << DIV_H / input-clk
22 * CLK_ENABLE: When it is unset the pwm controller will assert the duty counter reset and
31 * - Enabled changing when the duty_cycle bigger than 0% and less than 100%.
32 * - Polarity changing when the duty_cycle bigger than 0% and less than 100%.
35 * - When changing both duty cycle and period, we cannot prevent in
38 * - Disabling the PWM doesn't complete the current period.
41 * - When only changing one of duty cycle or period, our pwm controller will not
59 #include <linux/reset.h>
137 struct reset_control *reset; member
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/linux-6.12.1/drivers/power/reset/
Docelot-reset.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi MIPS SoC reset driver
48 u32 if_si_owner_bit = ctx->props->if_si_owner_bit; in ocelot_restart_handle()
50 /* Make sure the core is not protected from reset */ in ocelot_restart_handle()
51 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in ocelot_restart_handle()
52 ctx->props->vcore_protect, 0); in ocelot_restart_handle()
56 regmap_update_bits(ctx->cpu_ctrl, in ocelot_restart_handle()
63 writel(SOFT_CHIP_RST, ctx->base); in ocelot_restart_handle()
72 struct device *dev = &pdev->dev; in ocelot_reset_probe()
75 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in ocelot_reset_probe()
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/linux-6.12.1/drivers/mtd/nand/raw/
Dmpc5121_nfc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
108 struct nand_chip chip; member
124 struct nand_chip *chip = mtd_to_nand(mtd); in nfc_read() local
125 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); in nfc_read()
127 return in_be16(prv->regs + reg); in nfc_read()
133 struct nand_chip *chip = mtd_to_nand(mtd); in nfc_write() local
134 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); in nfc_write()
136 out_be16(prv->regs + reg, val); in nfc_write()
203 struct nand_chip *chip = mtd_to_nand(mtd); in mpc5121_nfc_irq() local
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/linux-6.12.1/Documentation/devicetree/bindings/mfd/
Daltera-a10sr.txt1 * Altera Arria10 Development Kit System Resource Chip
4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
7 System Resource chip
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
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/linux-6.12.1/Documentation/devicetree/bindings/net/wireless/
Dsilabs,wfx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jérôme Pouiller <jerome.pouiller@silabs.com>
14 Support for the Wifi chip WFxxx from Silicon Labs. Currently, the only device
16 https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf
22 Declaring the WFxxx chip in device tree is mandatory (usually, the VID/PID is
25 It is recommended to declare a mmc-pwrseq on SDIO host above WFx. Without
26 it, you may encounter issues during reboot. The mmc-pwrseq should be
27 compatible with mmc-pwrseq-simple. Please consult
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