Lines Matching +full:chip +full:- +full:reset
1 // SPDX-License-Identifier: ISC
18 #include "chip.h"
20 /* SOC Interconnect types (aka chip types) */
24 /* PL-368 DMP definitions */
84 /* chip core base & ramsize */
223 struct brcmf_chip_priv *chip; member
236 u32 reset);
237 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
246 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh)); in brcmf_chip_sb_corerev()
247 core->rev = SBCOREREV(regdata); in brcmf_chip_sb_corerev()
256 ci = core->chip; in brcmf_chip_sb_iscoreup()
257 address = CORE_SB(core->pub.base, sbtmstatelow); in brcmf_chip_sb_iscoreup()
258 regdata = ci->ops->read32(ci->ctx, address); in brcmf_chip_sb_iscoreup()
270 ci = core->chip; in brcmf_chip_ai_iscoreup()
271 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_iscoreup()
274 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL); in brcmf_chip_ai_iscoreup()
281 u32 prereset, u32 reset) in brcmf_chip_sb_coredisable() argument
286 ci = core->chip; in brcmf_chip_sb_coredisable()
287 base = core->pub.base; in brcmf_chip_sb_coredisable()
288 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
292 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
296 * (preserve core-specific bits) in brcmf_chip_sb_coredisable()
298 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
299 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_coredisable()
302 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
304 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)) in brcmf_chip_sb_coredisable()
307 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); in brcmf_chip_sb_coredisable()
311 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); in brcmf_chip_sb_coredisable()
313 val = ci->ops->read32(ci->ctx, in brcmf_chip_sb_coredisable()
316 ci->ops->write32(ci->ctx, in brcmf_chip_sb_coredisable()
318 val = ci->ops->read32(ci->ctx, in brcmf_chip_sb_coredisable()
321 SPINWAIT((ci->ops->read32(ci->ctx, in brcmf_chip_sb_coredisable()
326 /* set reset and reject while enabling the clocks */ in brcmf_chip_sb_coredisable()
329 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val); in brcmf_chip_sb_coredisable()
330 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
334 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); in brcmf_chip_sb_coredisable()
336 val = ci->ops->read32(ci->ctx, in brcmf_chip_sb_coredisable()
339 ci->ops->write32(ci->ctx, in brcmf_chip_sb_coredisable()
344 /* leave reset and reject asserted */ in brcmf_chip_sb_coredisable()
345 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_coredisable()
351 u32 prereset, u32 reset) in brcmf_chip_ai_coredisable() argument
356 ci = core->chip; in brcmf_chip_ai_coredisable()
358 /* if core is already in reset, skip reset */ in brcmf_chip_ai_coredisable()
359 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL); in brcmf_chip_ai_coredisable()
363 /* configure reset */ in brcmf_chip_ai_coredisable()
364 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, in brcmf_chip_ai_coredisable()
366 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_coredisable()
368 /* put in reset */ in brcmf_chip_ai_coredisable()
369 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, in brcmf_chip_ai_coredisable()
373 /* wait till reset is 1 */ in brcmf_chip_ai_coredisable()
374 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) != in brcmf_chip_ai_coredisable()
378 /* in-reset configure */ in brcmf_chip_ai_coredisable()
379 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, in brcmf_chip_ai_coredisable()
380 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK); in brcmf_chip_ai_coredisable()
381 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_coredisable()
385 u32 reset, u32 postreset) in brcmf_chip_sb_resetcore() argument
391 ci = core->chip; in brcmf_chip_sb_resetcore()
392 base = core->pub.base; in brcmf_chip_sb_resetcore()
401 * set reset while enabling the clock and in brcmf_chip_sb_resetcore()
404 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_resetcore()
407 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_resetcore()
411 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); in brcmf_chip_sb_resetcore()
413 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0); in brcmf_chip_sb_resetcore()
415 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate)); in brcmf_chip_sb_resetcore()
418 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata); in brcmf_chip_sb_resetcore()
421 /* clear reset and allow it to propagate throughout the core */ in brcmf_chip_sb_resetcore()
422 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_resetcore()
424 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_resetcore()
428 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_resetcore()
430 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_resetcore()
435 u32 reset, u32 postreset) in brcmf_chip_ai_resetcore() argument
442 ci = core->chip; in brcmf_chip_ai_resetcore()
444 /* special handle two D11 cores reset */ in brcmf_chip_ai_resetcore()
445 if (core->pub.id == BCMA_CORE_80211) { in brcmf_chip_ai_resetcore()
446 d11core2 = brcmf_chip_get_d11core(&ci->pub, 1); in brcmf_chip_ai_resetcore()
448 brcmf_dbg(INFO, "found two d11 cores, reset both\n"); in brcmf_chip_ai_resetcore()
455 brcmf_chip_ai_coredisable(core, prereset, reset); in brcmf_chip_ai_resetcore()
457 brcmf_chip_ai_coredisable(d11priv2, prereset, reset); in brcmf_chip_ai_resetcore()
460 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) & in brcmf_chip_ai_resetcore()
462 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0); in brcmf_chip_ai_resetcore()
471 while (ci->ops->read32(ci->ctx, in brcmf_chip_ai_resetcore()
472 d11priv2->wrapbase + BCMA_RESET_CTL) & in brcmf_chip_ai_resetcore()
474 ci->ops->write32(ci->ctx, in brcmf_chip_ai_resetcore()
475 d11priv2->wrapbase + BCMA_RESET_CTL, in brcmf_chip_ai_resetcore()
484 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, in brcmf_chip_ai_resetcore()
486 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_resetcore()
489 ci->ops->write32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL, in brcmf_chip_ai_resetcore()
491 ci->ops->read32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_resetcore()
512 return ERR_PTR(-ENOMEM); in brcmf_chip_add_core()
514 core->pub.id = coreid; in brcmf_chip_add_core()
515 core->pub.base = base; in brcmf_chip_add_core()
516 core->chip = ci; in brcmf_chip_add_core()
517 core->wrapbase = wrapbase; in brcmf_chip_add_core()
519 list_add_tail(&core->list, &ci->cores); in brcmf_chip_add_core()
520 return &core->pub; in brcmf_chip_add_core()
532 list_for_each_entry(core, &ci->cores, list) { in brcmf_chip_cores_check()
533 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-3d base 0x%08x wrap 0x%08x\n", in brcmf_chip_cores_check()
534 idx++, core->pub.id, core->pub.rev, core->pub.base, in brcmf_chip_cores_check()
535 core->wrapbase); in brcmf_chip_cores_check()
537 switch (core->pub.id) { in brcmf_chip_cores_check()
558 return -ENXIO; in brcmf_chip_cores_check()
563 return -ENODEV; in brcmf_chip_cores_check()
570 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg); in brcmf_chip_core_read32()
576 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val); in brcmf_chip_core_write32()
604 if (WARN_ON(sr->pub.rev < 4)) in brcmf_chip_socram_ramsize()
607 if (!brcmf_chip_iscoreup(&sr->pub)) in brcmf_chip_socram_ramsize()
608 brcmf_chip_resetcore(&sr->pub, 0, 0, 0); in brcmf_chip_socram_ramsize()
614 if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) { in brcmf_chip_socram_ramsize()
618 nb--; in brcmf_chip_socram_ramsize()
621 *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE)); in brcmf_chip_socram_ramsize()
624 if (sr->pub.rev >= 23) { in brcmf_chip_socram_ramsize()
639 switch (sr->chip->pub.chip) { in brcmf_chip_socram_ramsize()
641 if (sr->chip->pub.chiprev < 2) in brcmf_chip_socram_ramsize()
665 if (!brcmf_chip_iscoreup(&sysmem->pub)) in brcmf_chip_sysmem_ramsize()
666 brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0); in brcmf_chip_sysmem_ramsize()
679 /** Return the TCM-RAM size of the ARMCR4 core. */
712 switch (ci->pub.chip) { in brcmf_chip_tcm_rambase()
737 return (ci->pub.chiprev < 9) ? 0x180000 : 0x160000; in brcmf_chip_tcm_rambase()
749 brcmf_err("unknown chip: %s\n", ci->pub.name); in brcmf_chip_tcm_rambase()
762 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4); in brcmf_chip_get_raminfo()
765 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core); in brcmf_chip_get_raminfo()
766 ci->pub.rambase = brcmf_chip_tcm_rambase(ci); in brcmf_chip_get_raminfo()
767 if (ci->pub.rambase == INVALID_RAMBASE) { in brcmf_chip_get_raminfo()
769 return -EINVAL; in brcmf_chip_get_raminfo()
772 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM); in brcmf_chip_get_raminfo()
776 ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core); in brcmf_chip_get_raminfo()
777 ci->pub.rambase = brcmf_chip_tcm_rambase(ci); in brcmf_chip_get_raminfo()
778 if (ci->pub.rambase == INVALID_RAMBASE) { in brcmf_chip_get_raminfo()
780 return -EINVAL; in brcmf_chip_get_raminfo()
783 mem = brcmf_chip_get_core(&ci->pub, in brcmf_chip_get_raminfo()
787 return -ENOMEM; in brcmf_chip_get_raminfo()
791 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize, in brcmf_chip_get_raminfo()
792 &ci->pub.srsize); in brcmf_chip_get_raminfo()
796 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize, in brcmf_chip_get_raminfo()
797 ci->pub.srsize, ci->pub.srsize); in brcmf_chip_get_raminfo()
799 if (!ci->pub.ramsize) { in brcmf_chip_get_raminfo()
801 return -ENOMEM; in brcmf_chip_get_raminfo()
804 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) { in brcmf_chip_get_raminfo()
806 return -ENOMEM; in brcmf_chip_get_raminfo()
818 val = ci->ops->read32(ci->ctx, *eromaddr); in brcmf_chip_dmp_get_desc()
847 *eromaddr -= 4; in brcmf_chip_dmp_get_regaddr()
850 *eromaddr -= 4; in brcmf_chip_dmp_get_regaddr()
851 return -EILSEQ; in brcmf_chip_dmp_get_regaddr()
860 *eromaddr -= 4; in brcmf_chip_dmp_get_regaddr()
861 return -EFAULT; in brcmf_chip_dmp_get_regaddr()
868 *eromaddr -= 4; in brcmf_chip_dmp_get_regaddr()
872 /* skip upper 32-bit address descriptor */ in brcmf_chip_dmp_get_regaddr()
915 eromaddr = ci->ops->read32(ci->ctx, in brcmf_chip_dmp_erom_scan()
916 CORE_CC_REG(ci->pub.enum_base, eromptr)); in brcmf_chip_dmp_erom_scan()
935 return -EFAULT; in brcmf_chip_dmp_erom_scan()
958 core->rev = rev; in brcmf_chip_dmp_erom_scan()
982 regdata = ci->ops->read32(ci->ctx, in brcmf_chip_recognition()
983 CORE_CC_REG(ci->pub.enum_base, chipid)); in brcmf_chip_recognition()
986 return -ENODEV; in brcmf_chip_recognition()
989 ci->pub.chip = regdata & CID_ID_MASK; in brcmf_chip_recognition()
990 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT; in brcmf_chip_recognition()
993 brcmf_chip_name(ci->pub.chip, ci->pub.chiprev, in brcmf_chip_recognition()
994 ci->pub.name, sizeof(ci->pub.name)); in brcmf_chip_recognition()
995 brcmf_dbg(INFO, "found %s chip: %s\n", in brcmf_chip_recognition()
996 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name); in brcmf_chip_recognition()
999 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) { in brcmf_chip_recognition()
1000 brcmf_err("SB chip is not supported\n"); in brcmf_chip_recognition()
1001 return -ENODEV; in brcmf_chip_recognition()
1003 ci->iscoreup = brcmf_chip_sb_iscoreup; in brcmf_chip_recognition()
1004 ci->coredisable = brcmf_chip_sb_coredisable; in brcmf_chip_recognition()
1005 ci->resetcore = brcmf_chip_sb_resetcore; in brcmf_chip_recognition()
1023 ci->iscoreup = brcmf_chip_ai_iscoreup; in brcmf_chip_recognition()
1024 ci->coredisable = brcmf_chip_ai_coredisable; in brcmf_chip_recognition()
1025 ci->resetcore = brcmf_chip_ai_resetcore; in brcmf_chip_recognition()
1029 brcmf_err("chip backplane type %u is not supported\n", in brcmf_chip_recognition()
1031 return -ENODEV; in brcmf_chip_recognition()
1038 /* assure chip is passive for core access */ in brcmf_chip_recognition()
1039 brcmf_chip_set_passive(&ci->pub); in brcmf_chip_recognition()
1041 /* Call bus specific reset function now. Cores have been determined in brcmf_chip_recognition()
1042 * but further access may require a chip specific reset at this point. in brcmf_chip_recognition()
1044 if (ci->ops->reset) { in brcmf_chip_recognition()
1045 ci->ops->reset(ci->ctx, &ci->pub); in brcmf_chip_recognition()
1046 brcmf_chip_set_passive(&ci->pub); in brcmf_chip_recognition()
1049 return brcmf_chip_get_raminfo(&ci->pub); in brcmf_chip_recognition()
1052 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id) in brcmf_chip_disable_arm() argument
1059 core = brcmf_chip_get_core(&chip->pub, id); in brcmf_chip_disable_arm()
1072 val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL); in brcmf_chip_disable_arm()
1083 static int brcmf_chip_setup(struct brcmf_chip_priv *chip) in brcmf_chip_setup() argument
1092 pub = &chip->pub; in brcmf_chip_setup()
1093 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list); in brcmf_chip_setup()
1094 base = cc->pub.base; in brcmf_chip_setup()
1097 pub->cc_caps = chip->ops->read32(chip->ctx, in brcmf_chip_setup()
1099 pub->cc_caps_ext = chip->ops->read32(chip->ctx, in brcmf_chip_setup()
1105 if (pub->cc_caps & CC_CAP_PMU) { in brcmf_chip_setup()
1106 val = chip->ops->read32(chip->ctx, in brcmf_chip_setup()
1107 CORE_CC_REG(pmu->base, pmucapabilities)); in brcmf_chip_setup()
1108 pub->pmurev = val & PCAP_REV_MASK; in brcmf_chip_setup()
1109 pub->pmucaps = val; in brcmf_chip_setup()
1113 cc->pub.rev, pub->pmurev, pub->pmucaps); in brcmf_chip_setup()
1116 if (chip->ops->setup) in brcmf_chip_setup()
1117 ret = chip->ops->setup(chip->ctx, pub); in brcmf_chip_setup()
1125 struct brcmf_chip_priv *chip; in brcmf_chip_attach() local
1128 if (WARN_ON(!ops->read32)) in brcmf_chip_attach()
1129 err = -EINVAL; in brcmf_chip_attach()
1130 if (WARN_ON(!ops->write32)) in brcmf_chip_attach()
1131 err = -EINVAL; in brcmf_chip_attach()
1132 if (WARN_ON(!ops->prepare)) in brcmf_chip_attach()
1133 err = -EINVAL; in brcmf_chip_attach()
1134 if (WARN_ON(!ops->activate)) in brcmf_chip_attach()
1135 err = -EINVAL; in brcmf_chip_attach()
1137 return ERR_PTR(-EINVAL); in brcmf_chip_attach()
1139 chip = kzalloc(sizeof(*chip), GFP_KERNEL); in brcmf_chip_attach()
1140 if (!chip) in brcmf_chip_attach()
1141 return ERR_PTR(-ENOMEM); in brcmf_chip_attach()
1143 INIT_LIST_HEAD(&chip->cores); in brcmf_chip_attach()
1144 chip->num_cores = 0; in brcmf_chip_attach()
1145 chip->ops = ops; in brcmf_chip_attach()
1146 chip->ctx = ctx; in brcmf_chip_attach()
1147 chip->pub.enum_base = brcmf_chip_enum_base(devid); in brcmf_chip_attach()
1149 err = ops->prepare(ctx); in brcmf_chip_attach()
1153 err = brcmf_chip_recognition(chip); in brcmf_chip_attach()
1157 err = brcmf_chip_setup(chip); in brcmf_chip_attach()
1161 return &chip->pub; in brcmf_chip_attach()
1164 brcmf_chip_detach(&chip->pub); in brcmf_chip_attach()
1170 struct brcmf_chip_priv *chip; in brcmf_chip_detach() local
1174 chip = container_of(pub, struct brcmf_chip_priv, pub); in brcmf_chip_detach()
1175 list_for_each_entry_safe(core, tmp, &chip->cores, list) { in brcmf_chip_detach()
1176 list_del(&core->list); in brcmf_chip_detach()
1179 kfree(chip); in brcmf_chip_detach()
1184 struct brcmf_chip_priv *chip; in brcmf_chip_get_d11core() local
1187 chip = container_of(pub, struct brcmf_chip_priv, pub); in brcmf_chip_get_d11core()
1188 list_for_each_entry(core, &chip->cores, list) { in brcmf_chip_get_d11core()
1189 if (core->pub.id == BCMA_CORE_80211) { in brcmf_chip_get_d11core()
1190 if (unit-- == 0) in brcmf_chip_get_d11core()
1191 return &core->pub; in brcmf_chip_get_d11core()
1199 struct brcmf_chip_priv *chip; in brcmf_chip_get_core() local
1202 chip = container_of(pub, struct brcmf_chip_priv, pub); in brcmf_chip_get_core()
1203 list_for_each_entry(core, &chip->cores, list) in brcmf_chip_get_core()
1204 if (core->pub.id == coreid) in brcmf_chip_get_core()
1205 return &core->pub; in brcmf_chip_get_core()
1212 struct brcmf_chip_priv *chip; in brcmf_chip_get_chipcommon() local
1215 chip = container_of(pub, struct brcmf_chip_priv, pub); in brcmf_chip_get_chipcommon()
1216 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list); in brcmf_chip_get_chipcommon()
1217 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON)) in brcmf_chip_get_chipcommon()
1219 return &cc->pub; in brcmf_chip_get_chipcommon()
1228 if (cc->rev >= 35 && in brcmf_chip_get_pmu()
1229 pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) { in brcmf_chip_get_pmu()
1244 return core->chip->iscoreup(core); in brcmf_chip_iscoreup()
1247 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset) in brcmf_chip_coredisable() argument
1252 core->chip->coredisable(core, prereset, reset); in brcmf_chip_coredisable()
1255 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset, in brcmf_chip_resetcore() argument
1261 core->chip->resetcore(core, prereset, reset, postreset); in brcmf_chip_resetcore()
1265 brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip) in brcmf_chip_cm3_set_passive() argument
1270 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3); in brcmf_chip_cm3_set_passive()
1271 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211); in brcmf_chip_cm3_set_passive()
1276 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM); in brcmf_chip_cm3_set_passive()
1280 if (chip->pub.chip == BRCM_CC_43430_CHIP_ID || in brcmf_chip_cm3_set_passive()
1281 chip->pub.chip == CY_CC_43439_CHIP_ID) { in brcmf_chip_cm3_set_passive()
1288 static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip) in brcmf_chip_cm3_set_active() argument
1292 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM); in brcmf_chip_cm3_set_active()
1294 brcmf_err("SOCRAM core is down after reset?\n"); in brcmf_chip_cm3_set_active()
1298 chip->ops->activate(chip->ctx, &chip->pub, 0); in brcmf_chip_cm3_set_active()
1300 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3); in brcmf_chip_cm3_set_active()
1307 brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip) in brcmf_chip_cr4_set_passive() argument
1312 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4); in brcmf_chip_cr4_set_passive()
1315 * Releasing reset ourselves breaks BCM4387 in weird ways. in brcmf_chip_cr4_set_passive()
1317 for (i = 0; (core = brcmf_chip_get_d11core(&chip->pub, i)); i++) in brcmf_chip_cr4_set_passive()
1323 static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec) in brcmf_chip_cr4_set_active() argument
1327 chip->ops->activate(chip->ctx, &chip->pub, rstvec); in brcmf_chip_cr4_set_active()
1330 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4); in brcmf_chip_cr4_set_active()
1337 brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip) in brcmf_chip_ca7_set_passive() argument
1341 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CA7); in brcmf_chip_ca7_set_passive()
1343 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211); in brcmf_chip_ca7_set_passive()
1350 static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec) in brcmf_chip_ca7_set_active() argument
1354 chip->ops->activate(chip->ctx, &chip->pub, rstvec); in brcmf_chip_ca7_set_active()
1357 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7); in brcmf_chip_ca7_set_active()
1365 struct brcmf_chip_priv *chip; in brcmf_chip_set_passive() local
1370 chip = container_of(pub, struct brcmf_chip_priv, pub); in brcmf_chip_set_passive()
1373 brcmf_chip_cr4_set_passive(chip); in brcmf_chip_set_passive()
1378 brcmf_chip_ca7_set_passive(chip); in brcmf_chip_set_passive()
1383 brcmf_chip_cm3_set_passive(chip); in brcmf_chip_set_passive()
1390 struct brcmf_chip_priv *chip; in brcmf_chip_set_active() local
1395 chip = container_of(pub, struct brcmf_chip_priv, pub); in brcmf_chip_set_active()
1398 return brcmf_chip_cr4_set_active(chip, rstvec); in brcmf_chip_set_active()
1401 return brcmf_chip_ca7_set_active(chip, rstvec); in brcmf_chip_set_active()
1404 return brcmf_chip_cm3_set_active(chip); in brcmf_chip_set_active()
1412 struct brcmf_chip_priv *chip; in brcmf_chip_sr_capable() local
1418 if (pub->pmurev < 17) in brcmf_chip_sr_capable()
1421 base = brcmf_chip_get_chipcommon(pub)->base; in brcmf_chip_sr_capable()
1422 chip = container_of(pub, struct brcmf_chip_priv, pub); in brcmf_chip_sr_capable()
1424 switch (pub->chip) { in brcmf_chip_sr_capable()
1436 addr = CORE_CC_REG(pmu->base, chipcontrol_addr); in brcmf_chip_sr_capable()
1437 chip->ops->write32(chip->ctx, addr, 3); in brcmf_chip_sr_capable()
1438 addr = CORE_CC_REG(pmu->base, chipcontrol_data); in brcmf_chip_sr_capable()
1439 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()
1444 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()
1450 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()
1455 addr = CORE_CC_REG(pmu->base, retention_ctl); in brcmf_chip_sr_capable()
1456 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()
1460 addr = CORE_CC_REG(pmu->base, pmucapabilities_ext); in brcmf_chip_sr_capable()
1461 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()
1465 addr = CORE_CC_REG(pmu->base, retention_ctl); in brcmf_chip_sr_capable()
1466 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()