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/linux-6.12.1/drivers/clk/ingenic/
Dcgu.c3 * Ingenic SoC CGU driver
23 #include "cgu.h"
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
35 * @cgu: reference to the CGU whose registers should be read
39 * caller must hold cgu->lock.
44 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, in ingenic_cgu_gate_get() argument
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
53 * @cgu: reference to the CGU whose registers should be modified
59 * The caller must hold cgu->lock.
62 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, in ingenic_cgu_gate_set() argument
[all …]
DKconfig9 bool "Ingenic JZ4740 CGU driver"
13 Support the clocks provided by the CGU hardware on Ingenic JZ4740
19 bool "Ingenic JZ4755 CGU driver"
23 Support the clocks provided by the CGU hardware on Ingenic JZ4755
29 bool "Ingenic JZ4725B CGU driver"
33 Support the clocks provided by the CGU hardware on Ingenic JZ4725B
39 bool "Ingenic JZ4760 CGU driver"
43 Support the clocks provided by the CGU hardware on Ingenic JZ4760
49 bool "Ingenic JZ4770 CGU driver"
53 Support the clocks provided by the CGU hardware on Ingenic JZ4770
[all …]
Dcgu.h3 * Ingenic SoC CGU driver
19 * @reg: the offset of the PLL's control register within the CGU
42 * @bypass_reg: the offset of the bypass control register within the CGU
49 * @set_rate_hook: hook called immediately after updating the CGU register,
72 * @reg: offset of the mux control register within the CGU
85 * @reg: offset of the divider control register within the CGU
122 * @reg: offset of the gate control register within the CGU
148 * within the clock_info array of the CGU, or -1 in entries
191 * struct ingenic_cgu - data about the CGU
192 * @np: the device tree node that caused the CGU to be probed
[all …]
DMakefile2 obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
3 obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
4 obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o
5 obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
6 obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
7 obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
8 obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
9 obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
10 obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o
Dx1000-cgu.c3 * X1000 SoC CGU driver
13 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
15 #include "cgu.h"
18 /* CGU register offsets */
62 static struct ingenic_cgu *cgu; variable
70 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate()
122 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate()
124 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
127 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
129 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate()
[all …]
Djz4780-cgu.c3 * Ingenic JZ4780 SoC CGU driver
16 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
18 #include "cgu.h"
21 /* CGU register offsets */
103 static struct ingenic_cgu *cgu; variable
111 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
175 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
178 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
180 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
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Djz4755-cgu.c3 * Ingenic JZ4755 SoC CGU driver
4 * Heavily based on JZ4725b CGU driver
14 #include <dt-bindings/clock/ingenic,jz4755-cgu.h>
16 #include "cgu.h"
19 /* CGU register offsets */
30 static struct ingenic_cgu *cgu; variable
329 cgu = ingenic_cgu_new(jz4755_cgu_clocks, in jz4755_cgu_init()
331 if (!cgu) { in jz4755_cgu_init()
332 pr_err("%s: failed to initialise CGU\n", __func__); in jz4755_cgu_init()
336 retval = ingenic_cgu_register_clocks(cgu); in jz4755_cgu_init()
[all …]
Dx1830-cgu.c3 * X1830 SoC CGU driver
12 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
14 #include "cgu.h"
17 /* CGU register offsets */
55 static struct ingenic_cgu *cgu; variable
59 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_enable()
60 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_enable()
69 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_disable()
70 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_disable()
78 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_is_enabled()
[all …]
Djz4740-cgu.c3 * Ingenic JZ4740 SoC CGU driver
14 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
16 #include "cgu.h"
19 /* CGU register offsets */
48 static struct ingenic_cgu *cgu; variable
258 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init()
260 if (!cgu) { in jz4740_cgu_init()
261 pr_err("%s: failed to initialise CGU\n", __func__); in jz4740_cgu_init()
265 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init()
267 pr_err("%s: failed to register CGU Clocks\n", __func__); in jz4740_cgu_init()
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Djz4725b-cgu.c3 * Ingenic JZ4725B SoC CGU driver
13 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
15 #include "cgu.h"
18 /* CGU register offsets */
33 static struct ingenic_cgu *cgu; variable
260 cgu = ingenic_cgu_new(jz4725b_cgu_clocks, in jz4725b_cgu_init()
262 if (!cgu) { in jz4725b_cgu_init()
263 pr_err("%s: failed to initialise CGU\n", __func__); in jz4725b_cgu_init()
267 retval = ingenic_cgu_register_clocks(cgu); in jz4725b_cgu_init()
269 pr_err("%s: failed to register CGU Clocks\n", __func__); in jz4725b_cgu_init()
[all …]
Djz4770-cgu.c3 * JZ4770 SoC CGU driver
13 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
15 #include "cgu.h"
49 static struct ingenic_cgu *cgu; variable
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dingenic,cgu.yaml4 $id: http://devicetree.org/schemas/clock/ingenic,cgu.yaml#
7 title: Ingenic SoCs CGU
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4755-cgu
26 - ingenic,jz4760-cgu
27 - ingenic,jz4760b-cgu
28 - ingenic,jz4770-cgu
29 - ingenic,jz4780-cgu
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Dlpc1850-ccu.txt3 Each CGU base clock has several clock branches which can be turned on
23 from the CGU to the specific CCU. See mapping of base clocks
27 from the CGU to the specific CCU. Valid CCU clock names:
47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
50 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
62 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
63 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
[all …]
Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
3 The CGU generates multiple independent clocks for the core and the
9 The CGU selects the inputs to the clock generators from multiple
23 Should be "nxp,lpc1850-cgu"
32 sources to the CGU. The list shall be in the following
36 number provided by the CGU.
39 the clocks provided by the CGU.
41 Which base clocks that are available on the CGU depends on the
116 cgu: clock-controller@40050000 {
117 compatible = "nxp,lpc1850-cgu";
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Dintel,cgu-lgm.yaml4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
7 title: Intel Lightning Mountain SoC's Clock Controller(CGU)
13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
14 all means to access the CGU hardware module in order to generate a series
23 const: intel,cgu-lgm
40 cgu: clock-controller@e0200000 {
41 compatible = "intel,cgu-lgm";
/linux-6.12.1/arch/mips/boot/dts/ingenic/
Djz4770.dtsi2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
19 clocks = <&cgu JZ4770_CLK_CCLK>;
53 cgu: jz4770-cgu@10000000 { label
54 compatible = "ingenic,jz4770-cgu", "simple-mfd";
69 clocks = <&cgu JZ4770_CLK_OTG_PHY>;
84 clocks = <&cgu JZ4770_CLK_RTC>,
85 <&cgu JZ4770_CLK_EXT>,
86 <&cgu JZ4770_CLK_PCLK>;
241 clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>;
257 clocks = <&cgu JZ4770_CLK_AIC>;
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Djz4740.dtsi2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
19 clocks = <&cgu JZ4740_CLK_CCLK>;
53 cgu: jz4740-cgu@10000000 { label
54 compatible = "ingenic,jz4740-cgu";
72 clocks = <&cgu JZ4740_CLK_RTC>,
73 <&cgu JZ4740_CLK_EXT>,
74 <&cgu JZ4740_CLK_PCLK>,
75 <&cgu JZ4740_CLK_TCU>;
114 clocks = <&cgu JZ4740_CLK_RTC>;
195 clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2S>;
[all …]
Djz4780.dtsi2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
20 clocks = <&cgu JZ4780_CLK_CPU>;
29 clocks = <&cgu JZ4780_CLK_CORE1>;
63 cgu: jz4780-cgu@10000000 { label
64 compatible = "ingenic,jz4780-cgu", "simple-mfd";
79 clocks = <&cgu JZ4780_CLK_OTG1>;
105 clocks = <&cgu JZ4780_CLK_RTCLK>,
106 <&cgu JZ4780_CLK_EXCLK>,
107 <&cgu JZ4780_CLK_PCLK>;
156 clocks = <&cgu JZ4780_CLK_RTCLK>;
[all …]
Dx1000.dtsi3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
20 clocks = <&cgu X1000_CLK_CPU>;
54 cgu: x1000-cgu@10000000 { label
55 compatible = "ingenic,x1000-cgu", "simple-mfd";
70 clocks = <&cgu X1000_CLK_OTGPHY>;
96 clocks = <&cgu X1000_CLK_OST>;
112 clocks = <&cgu X1000_CLK_RTCLK>,
113 <&cgu X1000_CLK_EXCLK>,
114 <&cgu X1000_CLK_PCLK>,
115 <&cgu X1000_CLK_TCU>;
[all …]
Dx1830.dtsi3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
20 clocks = <&cgu X1830_CLK_CPU>;
54 cgu: x1830-cgu@10000000 { label
55 compatible = "ingenic,x1830-cgu", "simple-mfd";
70 clocks = <&cgu X1830_CLK_OTGPHY>;
89 clocks = <&cgu X1830_CLK_OST>;
105 clocks = <&cgu X1830_CLK_RTCLK>,
106 <&cgu X1830_CLK_EXCLK>,
107 <&cgu X1830_CLK_PCLK>,
108 <&cgu X1830_CLK_TCU>;
[all …]
Djz4725b.dtsi2 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
19 clocks = <&cgu JZ4725B_CLK_CCLK>;
53 cgu: clock-controller@10000000 { label
54 compatible = "ingenic,jz4725b-cgu";
72 clocks = <&cgu JZ4725B_CLK_RTC>,
73 <&cgu JZ4725B_CLK_EXT>,
74 <&cgu JZ4725B_CLK_PCLK>,
75 <&cgu JZ4725B_CLK_TCU>;
123 clocks = <&cgu JZ4725B_CLK_RTC>;
201 clocks = <&cgu JZ4725B_CLK_AIC>, <&cgu JZ4725B_CLK_I2S>;
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Dgcw0.dts440 &cgu {
451 <&cgu JZ4770_CLK_PLL1>,
452 <&cgu JZ4770_CLK_GPU>,
453 <&cgu JZ4770_CLK_RTC>,
454 <&cgu JZ4770_CLK_UHC>,
455 <&cgu JZ4770_CLK_LPCLK_MUX>,
456 <&cgu JZ4770_CLK_MMC0_MUX>,
457 <&cgu JZ4770_CLK_MMC1_MUX>;
460 <&cgu JZ4770_CLK_PLL0>,
461 <&cgu JZ4770_CLK_OSC32K>,
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mips/lantiq/
Dlantiq,cgu.yaml4 $id: http://devicetree.org/schemas/mips/lantiq/lantiq,cgu.yaml#
7 title: Lantiq Xway SoC series Clock Generation Unit (CGU)
16 - lantiq,cgu-xway
29 cgu@103000 {
30 compatible = "lantiq,cgu-xway";
/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/
Dlpc18xx.dtsi16 #include "dt-bindings/clock/lpc18xx-cgu.h"
165 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
232 cgu: clock-controller@40050000 { label
233 compatible = "nxp,lpc1850-cgu";
243 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
244 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
245 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
246 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
257 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
258 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
[all …]
/linux-6.12.1/drivers/pinctrl/
Dpinctrl-xway.c126 MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
128 MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
129 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
137 MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
138 MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
198 GRP_MUX("clkout0", CGU, ase_pins_clkout0),
199 GRP_MUX("clkout1", CGU, ase_pins_clkout1),
200 GRP_MUX("clkout2", CGU, ase_pins_clkout2),
228 {"cgu", ARRAY_AND_SIZE(ase_cgu_grps)},
245 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, MII),
[all …]

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