| /linux-6.12.1/drivers/pwm/ |
| D | pwm-stm32-lp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer PWM driver
9 * Inspired by Gerald Baeza's pwm-stm32 driver
13 #include <linux/mfd/stm32-lptimer.h>
21 struct clk *clk; member
30 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
39 u32 val, mask, cfgr, presc = 0; in stm32_pwm_lp_apply() local
46 if (!state->enabled) { in stm32_pwm_lp_apply()
49 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); in stm32_pwm_lp_apply()
53 clk_disable(priv->clk); in stm32_pwm_lp_apply()
[all …]
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| /linux-6.12.1/drivers/mmc/host/ |
| D | mmci_stm32_sdmmc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
84 struct sdmmc_idma *idma = host->dma_priv; in sdmmc_idma_validate_data()
85 struct device *dev = mmc_dev(host->mmc); in sdmmc_idma_validate_data()
93 idma->use_bounce_buffer = false; in sdmmc_idma_validate_data()
94 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
95 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
96 !IS_ALIGNED(sg->length, in sdmmc_idma_validate_data()
97 host->variant->stm32_idmabsize_align)) { in sdmmc_idma_validate_data()
[all …]
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| /linux-6.12.1/drivers/rtc/ |
| D | rtc-stm32.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 #include <linux/pinctrl/pinconf-generic.h>
146 u16 cfgr; member
172 struct clk *pclk;
173 struct clk *rtc_ck;
176 struct clk *clk_lsco;
189 const struct stm32_rtc_registers *regs = &rtc->data->regs; in stm32_rtc_wpr_unlock()
191 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); in stm32_rtc_wpr_unlock()
[all …]
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| /linux-6.12.1/drivers/memory/ |
| D | stm32-fmc2-ebi.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
195 struct clk *clk; member
206 u32 cfgr; member
210 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
248 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
255 return -EINVAL; in stm32_fmc2_ebi_check_mux()
265 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_waitcfg()
272 return -EINVAL; in stm32_fmc2_ebi_check_waitcfg()
282 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_sync_trans()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/dma/ |
| D | snps,dw-axi-dmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
24 - starfive,jh8100-axi-dma
[all …]
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| /linux-6.12.1/sound/soc/stm/ |
| D | stm32_i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
205 * struct stm32_i2s_data - private data of I2S
238 struct clk *i2sclk;
[all …]
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| /linux-6.12.1/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
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| /linux-6.12.1/drivers/pinctrl/ |
| D | pinctrl-at91-pio4.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
11 #include <linux/clk.h>
21 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
80 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
107 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
109 * @clk: clock of the controller.
131 struct clk *clk; member
145 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; member
[all …]
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| /linux-6.12.1/arch/riscv/boot/dts/sophgo/ |
| D | cv18xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <25000000>;
24 d-cache-block-size = <64>;
[all …]
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| /linux-6.12.1/arch/arc/boot/dts/ |
| D | hsdk.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
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| /linux-6.12.1/arch/riscv/boot/dts/thead/ |
| D | th1520.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
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| /linux-6.12.1/arch/riscv/boot/dts/canaan/ |
| D | k210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
21 * Since this is a non-ratified draft specification, the kernel does not
[all …]
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| /linux-6.12.1/sound/soc/atmel/ |
| D | mchp-pdmc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
9 #include <dt-bindings/sound/microchip,pdmc.h>
12 #include <linux/clk.h>
24 * ---- PDMC Register map ----
37 * ---- Control Register (Write-only) ----
42 * ---- Mode Register (Read/Write) ----
66 * ---- Configuration Register (Read/Write) ----
75 * ---- Interrupt Enable/Disable/Mask/Status Registers ----
85 * ---- Version Register (Read-only) ----
[all …]
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| /linux-6.12.1/arch/riscv/boot/dts/starfive/ |
| D | jh7110.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
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| /linux-6.12.1/drivers/net/ethernet/freescale/ |
| D | fec_main.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
52 #include <linux/clk.h>
194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, },
195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, },
196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, },
197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, },
198 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, },
[all …]
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| /linux-6.12.1/drivers/dma/dw-axi-dmac/ |
| D | dw-axi-dmac-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
15 #include <linux/dma-mapping.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include "dw-axi-dmac.h"
34 #include "../virt-dma.h"
57 iowrite32(val, chip->regs + reg); in axi_dma_iowrite32()
62 return ioread32(chip->regs + reg); in axi_dma_ioread32()
68 iowrite64(val, chip->regs + reg); in axi_dma_iowrite64()
73 return ioread64(chip->regs + reg); in axi_dma_ioread64()
[all …]
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