| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 51 * DOC: CDCLK / RAWCLK
56 * are the core display clock (CDCLK) and RAWCLK.
58 * CDCLK clocks most of the display pipe logic, and thus its frequency
63 * On several platforms the CDCLK frequency can be changed dynamically
65 * Typically changes to the CDCLK frequency require all the display pipes
68 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
69 * DMC will not change the active CDCLK frequency however, so that part
72 * There are multiple components involved in the generation of the CDCLK
75 * - We have the CDCLK PLL, which generates an output clock based on a
84 * As such, the resulting CDCLK frequency can be calculated with the
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| D | intel_cdclk.h | 19 unsigned int cdclk, vco, ref, bypass; member
29 * Logical configuration of cdclk (used for all scaling,
36 * Actual configuration of cdclk, can be different from the
41 /* minimum acceptable cdclk to satisfy bandwidth requirements */
43 /* minimum acceptable cdclk for each pipe */
51 /* forced minimum cdclk for glk+ audio w/a */
57 /* update cdclk with pipes disabled */
91 …k_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
93 …k_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
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| D | intel_audio.c | 441 unsigned int fec_coeff, cdclk, vdsc_bppx16; in calc_hblank_early_prog() local
449 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
456 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", in calc_hblank_early_prog()
457 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); in calc_hblank_early_prog()
459 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) in calc_hblank_early_prog()
468 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
469 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
904 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
907 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
915 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
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| D | hsw_ips.c | 204 * the increased cdclk requirement into account when in hsw_crtc_state_ips_capable()
205 * calculating the new cdclk. in hsw_crtc_state_ips_capable()
207 * Should measure whether using a lower cdclk w/o IPS in hsw_crtc_state_ips_capable()
210 crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
248 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in hsw_ips_compute_config()
249 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
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| D | intel_display_core.h | 123 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
294 /* Display CDCLK functions */
295 const struct intel_cdclk_funcs *cdclk; member
343 /* The current hardware cdclk configuration */
346 /* cdclk, divider, and ratio table from bspec */
354 } cdclk; member
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| D | intel_atomic_plane.c | 287 * No need to check against the cdclk state if in intel_plane_calc_min_cdclk()
288 * the min cdclk for the plane doesn't increase. in intel_plane_calc_min_cdclk()
290 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
292 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
303 * No need to recalculate the cdclk state if in intel_plane_calc_min_cdclk()
304 * the min cdclk for the pipe doesn't increase. in intel_plane_calc_min_cdclk()
306 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
308 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
315 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", in intel_plane_calc_min_cdclk()
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| D | intel_bw.c | 1305 * No need to check against the cdclk state if in intel_bw_calc_min_cdclk()
1306 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1308 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
1310 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1320 * No need to recalculate the cdclk state if in intel_bw_calc_min_cdclk()
1321 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1323 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
1325 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1331 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n", in intel_bw_calc_min_cdclk()
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| D | intel_display_driver.c | 90 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()
93 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
94 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
453 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_display_driver_probe_nogem()
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| D | intel_pmdemand.c | 286 (new_cdclk_state->actual.cdclk != in intel_pmdemand_needs_update()
287 old_cdclk_state->actual.cdclk || in intel_pmdemand_needs_update()
342 DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000); in intel_pmdemand_atomic_check()
349 * Active_PLLs starts with 1 because of CDCLK PLL. in intel_pmdemand_atomic_check()
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| D | intel_dp_aux.c | 101 * The clock divider is based off the cdclk or PCH rawclk, and would in ilk_get_aux_clock_divider()
102 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and in ilk_get_aux_clock_divider()
106 freq = display->cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
134 * derive the clock from CDCLK automatically). We still implement the in skl_get_aux_clock_divider()
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| D | intel_dsi.c | 67 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; in intel_dsi_mode_valid()
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| D | intel_modeset_setup.c | 158 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_crtc_disable_noatomic_complete()
699 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_readout_hw_state()
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| D | intel_backlight.c | 1096 clock = KHz(i915->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1114 clock = KHz(i915->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
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| D | i9xx_plane.c | 381 * of cdclk when the sprite plane is enabled on the in i9xx_plane_ratio()
383 * never allowed to exceed 80% of cdclk. Let's just go in i9xx_plane_ratio()
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| D | intel_display_power.c | 1168 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); in hsw_assert_cdclk()
1347 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
1659 /* 4. Enable CDCLK. */ in icl_display_core_init()
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| D | intel_dvo.c | 226 int max_dotclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq; in intel_dvo_mode_valid()
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| D | intel_dpll_mgr.c | 1477 /* DPLL0 is always enabled since it drives CDCLK */ in skl_ddi_dpll0_get_hw_state()
1978 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
3963 * DVFS pre sequence would be here, but in our driver the cdclk code in combo_pll_enable()
3986 * DVFS pre sequence would be here, but in our driver the cdclk code in tbt_pll_enable()
4011 * DVFS pre sequence would be here, but in our driver the cdclk code in mg_pll_enable()
4028 * DVFS pre sequence would be here, but in our driver the cdclk code in icl_pll_disable()
4077 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
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| D | intel_tv.c | 964 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_tv_mode_valid()
1302 * oversample clock on gen3, cdclk on gen4). Once the pipe in intel_tv_compute_config()
1331 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive); in intel_tv_compute_config()
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-exynos-audss.c | 128 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
188 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
190 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
191 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
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| D | clk-s5pv210-audss.c | 70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
119 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | samsung,exynos-audss-clock.yaml | 52 - const: cdclk
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
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| /linux-6.12.1/sound/hda/ |
| D | hdac_i915.c | 26 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
27 * BCLK = CDCLK * M / N
54 default: /* default CDCLK 450MHz */ in snd_hdac_i915_set_bclk()
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| /linux-6.12.1/include/dt-bindings/sound/ |
| D | samsung-i2s.h | 5 #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */
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| /linux-6.12.1/Documentation/devicetree/bindings/sound/ |
| D | samsung-i2s.yaml | 115 description: Names of the CDCLK I2S output clocks.
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| /linux-6.12.1/arch/arm/boot/dts/samsung/ |
| D | s3c64xx-pinctrl.dtsi | 334 i2s0_cdclk: i2s0-cdclk-pins {
346 i2s1_cdclk: i2s1-cdclk-pins {
360 i2s2_cdclk: i2s2-cdclk-pins {
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