Lines Matching full:cdclk
51 * DOC: CDCLK / RAWCLK
56 * are the core display clock (CDCLK) and RAWCLK.
58 * CDCLK clocks most of the display pipe logic, and thus its frequency
63 * On several platforms the CDCLK frequency can be changed dynamically
65 * Typically changes to the CDCLK frequency require all the display pipes
68 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
69 * DMC will not change the active CDCLK frequency however, so that part
72 * There are multiple components involved in the generation of the CDCLK
75 * - We have the CDCLK PLL, which generates an output clock based on a
84 * As such, the resulting CDCLK frequency can be calculated with the
87 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
98 * Several methods exist to change the CDCLK frequency, which ones are
121 u8 (*calc_voltage_level)(int cdclk);
127 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
134 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
141 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
145 int cdclk) in intel_cdclk_calc_voltage_level() argument
147 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
153 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
159 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
165 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
171 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
177 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
183 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
198 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
212 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
215 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
218 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
223 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
237 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
243 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
247 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
261 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
267 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
271 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
384 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
390 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", in g33_get_cdclk()
392 cdclk_config->cdclk = 190476; in g33_get_cdclk()
405 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
408 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
411 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
414 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
421 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
424 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
463 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
469 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", in i965gm_get_cdclk()
471 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
491 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
494 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
498 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", in gm45_get_cdclk()
500 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
512 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
514 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
516 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
518 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
520 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
543 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in vlv_calc_voltage_level() argument
546 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ in vlv_calc_voltage_level()
548 else if (cdclk >= 266667) in vlv_calc_voltage_level()
558 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
571 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
597 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
629 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk() local
633 switch (cdclk) { in vlv_set_cdclk()
641 MISSING_CASE(cdclk); in vlv_set_cdclk()
646 * off and a CDCLK frequency other than the minimum, like when in vlv_set_cdclk()
666 "timed out waiting for CDclk change\n"); in vlv_set_cdclk()
669 if (cdclk == 400000) { in vlv_set_cdclk()
673 cdclk) - 1; in vlv_set_cdclk()
675 /* adjust cdclk divider */ in vlv_set_cdclk()
685 "timed out waiting for CDclk change\n"); in vlv_set_cdclk()
696 if (cdclk == 400000) in vlv_set_cdclk()
718 int cdclk = cdclk_config->cdclk; in chv_set_cdclk() local
722 switch (cdclk) { in chv_set_cdclk()
729 MISSING_CASE(cdclk); in chv_set_cdclk()
734 * off and a CDCLK frequency other than the minimum, like when in chv_set_cdclk()
750 "timed out waiting for CDclk change\n"); in chv_set_cdclk()
774 static u8 bdw_calc_voltage_level(int cdclk) in bdw_calc_voltage_level() argument
776 switch (cdclk) { in bdw_calc_voltage_level()
796 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
798 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
800 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
802 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
804 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
806 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
810 * at least what the CDCLK frequency requires. in bdw_get_cdclk()
813 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
816 static u32 bdw_cdclk_freq_sel(int cdclk) in bdw_cdclk_freq_sel() argument
818 switch (cdclk) { in bdw_cdclk_freq_sel()
820 MISSING_CASE(cdclk); in bdw_cdclk_freq_sel()
837 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk() local
846 "trying to change cdclk frequency with cdclk not enabled\n")) in bdw_set_cdclk()
852 "failed to inform pcode about cdclk change\n"); in bdw_set_cdclk()
868 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); in bdw_set_cdclk()
881 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
909 static u8 skl_calc_voltage_level(int cdclk) in skl_calc_voltage_level() argument
911 if (cdclk > 540000) in skl_calc_voltage_level()
913 else if (cdclk > 450000) in skl_calc_voltage_level()
915 else if (cdclk > 337500) in skl_calc_voltage_level()
969 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
979 cdclk_config->cdclk = 432000; in skl_get_cdclk()
982 cdclk_config->cdclk = 308571; in skl_get_cdclk()
985 cdclk_config->cdclk = 540000; in skl_get_cdclk()
988 cdclk_config->cdclk = 617143; in skl_get_cdclk()
997 cdclk_config->cdclk = 450000; in skl_get_cdclk()
1000 cdclk_config->cdclk = 337500; in skl_get_cdclk()
1003 cdclk_config->cdclk = 540000; in skl_get_cdclk()
1006 cdclk_config->cdclk = 675000; in skl_get_cdclk()
1017 * at least what the CDCLK frequency requires. in skl_get_cdclk()
1020 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
1024 static int skl_cdclk_decimal(int cdclk) in skl_cdclk_decimal() argument
1026 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
1031 bool changed = i915->display.cdclk.skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
1033 i915->display.cdclk.skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
1074 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1088 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1092 int cdclk, int vco) in skl_cdclk_freq_sel() argument
1094 switch (cdclk) { in skl_cdclk_freq_sel()
1097 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1118 int cdclk = cdclk_config->cdclk; in skl_set_cdclk() local
1124 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are in skl_set_cdclk()
1129 * minimum 308MHz CDCLK. in skl_set_cdclk()
1140 "Failed to inform PCU about cdclk change (%d)\n", ret); in skl_set_cdclk()
1144 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); in skl_set_cdclk()
1146 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1147 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1152 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1155 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1164 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1171 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1199 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1202 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1203 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1214 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1220 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1222 /* force cdclk programming */ in skl_sanitize_cdclk()
1223 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1225 dev_priv->display.cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1234 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1235 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1240 if (dev_priv->display.cdclk.skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1242 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1246 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1248 cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1251 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1252 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_init_hw()
1259 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1261 cdclk_config.cdclk = cdclk_config.bypass; in skl_cdclk_uninit_hw()
1263 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_uninit_hw()
1269 u32 cdclk; member
1276 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1277 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1278 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1279 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1280 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1285 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1286 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1287 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1292 { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1293 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1294 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1295 { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1296 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1297 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1299 { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1300 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1301 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1302 { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1303 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1304 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1306 { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
1307 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1308 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1309 { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1310 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1311 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1316 { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
1317 { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
1318 { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
1319 { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1320 { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1321 { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1323 { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
1324 { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
1325 { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
1326 { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1327 { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
1328 { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1330 { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1331 { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1332 { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1333 { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1334 { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1335 { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1340 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1341 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1342 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1344 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1345 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1346 { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1348 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1349 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1350 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1355 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1356 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1357 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1358 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1359 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1361 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1362 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1363 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1364 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1365 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1367 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1368 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1369 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1370 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1371 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1376 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1377 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1378 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1379 { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1380 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1381 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1383 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1384 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1385 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1386 { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1387 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1388 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1390 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1391 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1392 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1393 { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1394 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1395 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1400 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1401 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1402 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1403 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1404 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1405 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1406 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1407 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1408 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1409 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1410 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1411 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1412 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1417 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1418 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1419 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1420 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1421 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1422 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1427 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1428 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1429 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1430 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1431 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1432 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1433 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1434 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1435 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1436 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1437 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1438 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1439 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1440 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1441 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1442 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1443 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1444 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1445 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1446 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1447 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1452 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
1455 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1466 static int cdclk_divider(int cdclk, int vco, u16 waveform) in cdclk_divider() argument
1470 cdclk * cdclk_squash_len); in cdclk_divider()
1475 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1479 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1480 table[i].cdclk >= min_cdclk) in bxt_calc_cdclk()
1481 return table[i].cdclk; in bxt_calc_cdclk()
1484 "Cannot satisfy minimum cdclk %d with refclk %u\n", in bxt_calc_cdclk()
1485 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1489 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1491 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1494 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1498 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1499 table[i].cdclk == cdclk) in bxt_calc_cdclk_pll_vco()
1500 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1502 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1503 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1507 static u8 bxt_calc_voltage_level(int cdclk) in bxt_calc_voltage_level() argument
1509 return DIV_ROUND_UP(cdclk, 25000); in bxt_calc_voltage_level()
1512 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, in calc_voltage_level() argument
1518 if (cdclk <= voltage_level_max_cdclk[voltage_level]) in calc_voltage_level()
1522 MISSING_CASE(cdclk); in calc_voltage_level()
1526 static u8 icl_calc_voltage_level(int cdclk) in icl_calc_voltage_level() argument
1534 return calc_voltage_level(cdclk, in icl_calc_voltage_level()
1539 static u8 ehl_calc_voltage_level(int cdclk) in ehl_calc_voltage_level() argument
1552 return calc_voltage_level(cdclk, in ehl_calc_voltage_level()
1557 static u8 tgl_calc_voltage_level(int cdclk) in tgl_calc_voltage_level() argument
1566 return calc_voltage_level(cdclk, in tgl_calc_voltage_level()
1571 static u8 rplu_calc_voltage_level(int cdclk) in rplu_calc_voltage_level() argument
1580 return calc_voltage_level(cdclk, in rplu_calc_voltage_level()
1622 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but in bxt_de_pll_readout()
1658 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1692 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1695 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1703 * at least what the CDCLK frequency requires. in bxt_get_cdclk()
1706 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1718 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1723 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1735 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1745 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1747 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1752 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1763 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1765 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1770 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1789 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1813 int cdclk, int vco, u16 waveform) in bxt_cdclk_cd2x_div_sel() argument
1815 /* cdclk = vco / 2 / div{1,1.5,2,4} */ in bxt_cdclk_cd2x_div_sel()
1816 switch (cdclk_divider(cdclk, vco, waveform)) { in bxt_cdclk_cd2x_div_sel()
1819 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1834 int cdclk) in cdclk_squash_waveform() argument
1836 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1839 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1843 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1844 table[i].cdclk == cdclk) in cdclk_squash_waveform()
1847 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1848 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1855 if (i915->display.cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1856 i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1859 if (i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1865 if (i915->display.cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1866 i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1869 if (i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1912 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); in intel_mdclk_cdclk_ratio()
1942 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1943 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1951 old_div = cdclk_divider(old_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
1953 new_div = cdclk_divider(new_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
1967 * - If moving to a higher cdclk, the desired action is squashing. in cdclk_compute_crawl_and_squash_midpoint()
1968 * The mid cdclk config should have the new (squash) waveform. in cdclk_compute_crawl_and_squash_midpoint()
1969 * - If moving to a lower cdclk, the desired action is crawling. in cdclk_compute_crawl_and_squash_midpoint()
1970 * The mid cdclk config should have the new vco. in cdclk_compute_crawl_and_squash_midpoint()
1983 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * in cdclk_compute_crawl_and_squash_midpoint()
1989 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
1990 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); in cdclk_compute_crawl_and_squash_midpoint()
1991 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
1992 i915->display.cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
1993 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
2004 dev_priv->display.cdclk.hw.vco > 0; in pll_enable_wa_needed()
2011 int cdclk = cdclk_config->cdclk; in bxt_cdclk_ctl() local
2016 waveform = cdclk_squash_waveform(i915, cdclk); in bxt_cdclk_ctl()
2018 val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) | in bxt_cdclk_ctl()
2026 cdclk >= 500000) in bxt_cdclk_ctl()
2032 val |= skl_cdclk_decimal(cdclk); in bxt_cdclk_ctl()
2041 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk() local
2044 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2045 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
2046 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
2058 u16 waveform = cdclk_squash_waveform(dev_priv, cdclk); in _bxt_set_cdclk()
2074 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk() local
2101 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", in bxt_set_cdclk()
2102 ret, cdclk); in bxt_set_cdclk()
2106 if (DISPLAY_VER(dev_priv) >= 20 && cdclk < dev_priv->display.cdclk.hw.cdclk) in bxt_set_cdclk()
2109 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
2117 if (DISPLAY_VER(dev_priv) >= 20 && cdclk > dev_priv->display.cdclk.hw.cdclk) in bxt_set_cdclk()
2142 "PCode CDCLK freq set failed, (err %d, freq %d)\n", in bxt_set_cdclk()
2143 ret, cdclk); in bxt_set_cdclk()
2154 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2160 int cdclk, vco; in bxt_sanitize_cdclk() local
2163 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2165 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2166 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
2169 /* Make sure this is a legal cdclk value for the platform */ in bxt_sanitize_cdclk()
2170 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2171 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2174 /* Make sure the VCO is correct for the cdclk */ in bxt_sanitize_cdclk()
2175 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
2176 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
2185 expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE); in bxt_sanitize_cdclk()
2200 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2202 /* force cdclk programming */ in bxt_sanitize_cdclk()
2203 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2206 dev_priv->display.cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2215 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2216 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2219 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2223 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
2226 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); in bxt_cdclk_init_hw()
2227 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2229 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2236 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2238 cdclk_config.cdclk = cdclk_config.bypass; in bxt_cdclk_uninit_hw()
2241 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2247 * intel_cdclk_init_hw - Initialize CDCLK hardware
2250 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2253 * take care of turning CDCLK off/on as needed.
2264 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2267 * Uninitialize CDCLK. This is done only during the display core
2293 old_waveform = cdclk_squash_waveform(i915, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2294 new_waveform = cdclk_squash_waveform(i915, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2313 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
2314 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
2335 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2343 * @a: first CDCLK configuration
2344 * @b: second CDCLK configuration
2347 * True if CDCLK changed in a way that requires re-programming and
2353 return a->cdclk != b->cdclk || in intel_cdclk_clock_changed()
2359 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2362 * @a: first CDCLK configuration
2363 * @b: second CDCLK configuration
2366 * True if changing between the two CDCLK configurations
2386 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2393 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2394 * @a: first CDCLK configuration
2395 * @b: second CDCLK configuration
2398 * True if the CDCLK configurations don't match, false if they do.
2412 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2420 u16 cdclk, in intel_pcode_notify() argument
2430 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); in intel_pcode_notify()
2455 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2458 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2472 * Lock aux/gmbus while we change cdclk in case those in intel_set_cdclk()
2473 * functions use cdclk. Not all platforms/ports do, in intel_set_cdclk()
2502 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2503 "cdclk state doesn't match!\n")) { in intel_set_cdclk()
2504 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2516 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_pre_notify() local
2528 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_pre_notify()
2534 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, in intel_cdclk_pcode_pre_notify()
2535 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, in intel_cdclk_pcode_pre_notify()
2536 * which basically means we choose the maximum of old and new CDCLK, if we know both in intel_cdclk_pcode_pre_notify()
2539 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); in intel_cdclk_pcode_pre_notify()
2550 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_pre_notify()
2561 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_post_notify() local
2567 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2573 * set bits 25:16 to current CDCLK in intel_cdclk_pcode_post_notify()
2576 cdclk = new_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2587 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_post_notify()
2599 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; in intel_cdclk_is_decreasing_later()
2603 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2607 * new CDCLK state, if necessary.
2631 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2652 "Pre changing CDCLK to"); in intel_set_cdclk_pre_plane_update()
2656 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2660 * new CDCLK state, if necessary.
2680 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) in intel_set_cdclk_post_plane_update()
2688 "Post changing CDCLK to"); in intel_set_cdclk_post_plane_update()
2732 * cannot be higher than the VDSC clock (cdclk) in intel_vdsc_min_cdclk()
2734 * VDSC clock(cdclk) * 2 and so on. in intel_vdsc_min_cdclk()
2744 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock in intel_vdsc_min_cdclk()
2746 * We have already computed compressed_bpp, so now compute the min CDCLK that in intel_vdsc_min_cdclk()
2749 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) in intel_vdsc_min_cdclk()
2752 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits in intel_vdsc_min_cdclk()
2776 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in intel_crtc_compute_min_cdclk()
2780 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, in intel_crtc_compute_min_cdclk()
2782 * there may be audio corruption or screen corruption." This cdclk in intel_crtc_compute_min_cdclk()
2806 * "For DP audio configuration, cdclk frequency shall be set to in intel_crtc_compute_min_cdclk()
2808 * DP Link Frequency(MHz) | Cdclk frequency(MHz) in intel_crtc_compute_min_cdclk()
2825 * On Geminilake once the CDCLK gets as low as 79200 in intel_crtc_compute_min_cdclk()
2893 * CDCLK frequency is always high enough for audio. With a in intel_compute_min_cdclk()
2894 * single active pipe we can always change CDCLK frequency in intel_compute_min_cdclk()
2902 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2904 "required cdclk (%d kHz) exceeds max (%d kHz)\n", in intel_compute_min_cdclk()
2905 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2967 int min_cdclk, cdclk; in vlv_modeset_calc_cdclk() local
2973 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); in vlv_modeset_calc_cdclk()
2975 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2977 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2980 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2982 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2984 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2996 int min_cdclk, cdclk; in bdw_modeset_calc_cdclk() local
3002 cdclk = bdw_calc_cdclk(min_cdclk); in bdw_modeset_calc_cdclk()
3004 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
3006 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
3009 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
3011 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
3013 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
3032 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3043 * clock for eDP. This will affect cdclk as well. in skl_dpll0_vco()
3063 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
3071 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
3074 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
3076 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
3079 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
3082 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
3084 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
3097 int min_cdclk, min_voltage_level, cdclk, vco; in bxt_modeset_calc_cdclk() local
3107 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); in bxt_modeset_calc_cdclk()
3108 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
3111 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3114 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); in bxt_modeset_calc_cdclk()
3117 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3118 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
3121 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3123 intel_cdclk_calc_voltage_level(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
3136 * We can't change the cdclk frequency, but we still want to in fixed_modeset_calc_cdclk()
3138 * the actual cdclk frequency. in fixed_modeset_calc_cdclk()
3178 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
3197 * planes are part of the state. We can now compute the minimum cdclk in intel_cdclk_atomic_check()
3242 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
3325 "Can change cdclk via crawling and squashing\n"); in intel_modeset_calc_cdclk()
3330 "Can change cdclk via squashing\n"); in intel_modeset_calc_cdclk()
3335 "Can change cdclk via crawling\n"); in intel_modeset_calc_cdclk()
3340 "Can change cdclk cd2x divider with pipe %c active\n", in intel_modeset_calc_cdclk()
3344 /* All pipes must be switched off while we change the cdclk. */ in intel_modeset_calc_cdclk()
3345 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); in intel_modeset_calc_cdclk()
3352 "Modeset required for cdclk change\n"); in intel_modeset_calc_cdclk()
3365 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", in intel_modeset_calc_cdclk()
3366 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
3367 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
3378 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3394 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3397 * Determine the maximum CDCLK frequency the platform supports, and also
3398 * derive the maximum dot clock frequency the maximum CDCLK frequency
3404 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3405 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3407 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3409 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3410 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3412 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3414 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3416 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3421 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3425 * Use the lower (vco 8640) cdclk values as a in intel_update_max_cdclk()
3438 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3447 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3449 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3451 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3453 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3455 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3457 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3459 /* otherwise assume cdclk is fixed */ in intel_update_max_cdclk()
3460 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3463 dev_priv->display.cdclk.max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
3466 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3469 dev_priv->display.cdclk.max_dotclk_freq); in intel_update_max_cdclk()
3473 * intel_update_cdclk - Determine the current CDCLK frequency
3476 * Determine the current CDCLK frequency.
3480 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3483 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): in intel_update_cdclk()
3485 * of cdclk that generates 4MHz reference clock freq which is used to in intel_update_cdclk()
3486 * generate GMBus clock. This will vary with the cdclk freq. in intel_update_cdclk()
3490 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3591 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in i915_cdclk_info_show()
3592 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3593 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display.cdclk.max_dotclk_freq); in i915_cdclk_info_show()
3745 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3751 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3752 dev_priv->display.cdclk.table = xe2lpd_cdclk_table; in intel_init_cdclk_hooks()
3754 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3755 dev_priv->display.cdclk.table = xe2hpd_cdclk_table; in intel_init_cdclk_hooks()
3757 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3758 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3760 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3761 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3765 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3766 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3768 dev_priv->display.cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3769 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3771 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3772 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3775 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3776 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3778 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3779 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3781 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3782 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3784 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3785 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3787 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3789 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3791 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3793 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3795 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3797 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3799 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3801 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3803 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3805 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3807 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3809 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3811 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3813 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3815 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3817 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3819 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3821 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3823 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3825 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3827 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3829 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3831 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3833 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3836 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3838 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()