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/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dbaikal,bt1-apb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 APB-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
15 which routes them to the AXI-APB bridge. This interface is a single master
17 addressed APB slave devices. In case of any APB protocol collisions, slave
19 reported to the APB terminator (APB Errors Handler Block).
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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/linux-6.12.1/drivers/bus/
Dbt1-apb.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 APB-bus driver
37 * struct bt1_apb - Baikal-T1 APB EHB private data
39 * @regs: APB EHB registers map.
40 * @res: No-device error injection memory region.
42 * @rate: APB-bus reference clock rate.
43 * @pclk: APB-reference clock.
44 * @prst: APB domain reset line.
70 static inline unsigned long bt1_apb_n_to_timeout_us(struct bt1_apb *apb, u32 n) in bt1_apb_n_to_timeout_us() argument
74 do_div(timeout, apb->rate); in bt1_apb_n_to_timeout_us()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-$(CONFIG_ARM_CCI) += arm-cci.o
8 obj-$(CONFIG_ARM_INTEGRATOR_LM) += arm-integrator-lm.o
9 obj-$(CONFIG_HISILICON_LPC) += hisi_lpc.o
10 obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
11 obj-$(CONFIG_MOXTET) += moxtet.o
13 # DPAA2 fsl-mc bus
14 obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/
16 obj-$(CONFIG_BT1_APB) += bt1-apb.o
17 obj-$(CONFIG_BT1_AXI) += bt1-axi.o
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/linux-6.12.1/drivers/spi/
Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
58 if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN) in dw_spi_bt1_dirmap_create()
59 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
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/linux-6.12.1/Documentation/devicetree/bindings/ata/
Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dbaikal,bt1-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
18 performed by software. There four in- and four outbound iATU regions
22 - $ref: /schemas/pci/snps,dw-pcie.yaml#
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/linux-6.12.1/drivers/clk/baikal-t1/
Dccu-rst.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 CCU Resets interface driver
11 #define pr_fmt(fmt) "bt1-ccu-rst: " fmt
19 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/bt1-ccu.h>
24 #include "ccu-rst.h"
66 * Each AXI-bus clock divider is equipped with the corresponding clock-consumer
67 * domain reset (it's self-deasserted reset control).
84 * SATA reference clock domain and APB-bus domain are connected with the
85 * sefl-deasserted reset control, which can be activated via the corresponding
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Dclk-ccu-div.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers clock driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
18 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/bt1-ccu.h>
28 #include "ccu-div.h"
29 #include "ccu-rst.h"
124 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
127 * the later is clocking the AXI-bus between DDR controller and the Main
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Dclk-ccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL clocks driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
18 #include <linux/clk-provider.h>
25 #include <dt-bindings/clock/bt1-ccu.h>
27 #include "ccu-pll.h"
59 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
60 * DDR controller AXI-bus clocks. If they are gated the system will be
62 * of the corresponding subsystems. So until we aren't ready to re-initialize
93 return data->plls[idx]; in ccu_pll_find_desc()
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/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Dsnps,designware-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB I2C Controller
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 const: mscc,ocelot-i2c
28 - description: Generic Synopsys DesignWare I2C controller
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/linux-6.12.1/drivers/ata/
Dahci_dwc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #define DRV_NAME "ahci-dwc"
95 /* Baikal-T1 AHCI SATA specific registers */
127 struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; in ahci_bt1_init()
130 /* APB, application and reference clocks are required */ in ahci_bt1_init()
134 dev_err(&dpriv->pdev->dev, "No system clocks specified\n"); in ahci_bt1_init()
135 return -EINVAL; in ahci_bt1_init()
145 dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n"); in ahci_bt1_init()
151 dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n"); in ahci_bt1_init()
163 dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL); in ahci_dwc_get_resources()
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