1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #define DRV_NAME "ahci-dwc"
95 /* Baikal-T1 AHCI SATA specific registers */
127 	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;  in ahci_bt1_init()
130 	/* APB, application and reference clocks are required */  in ahci_bt1_init()
134 		dev_err(&dpriv->pdev->dev, "No system clocks specified\n");  in ahci_bt1_init()
135 		return -EINVAL;  in ahci_bt1_init()
145 		dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n");  in ahci_bt1_init()
151 		dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n");  in ahci_bt1_init()
163 	dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL);  in ahci_dwc_get_resources()
165 		return ERR_PTR(-ENOMEM);  in ahci_dwc_get_resources()
167 	dpriv->pdev = pdev;  in ahci_dwc_get_resources()
168 	dpriv->pdata = device_get_match_data(&pdev->dev);  in ahci_dwc_get_resources()
169 	if (!dpriv->pdata)  in ahci_dwc_get_resources()
170 		return ERR_PTR(-EINVAL);  in ahci_dwc_get_resources()
172 	hpriv = ahci_platform_get_resources(pdev, dpriv->pdata->pflags);  in ahci_dwc_get_resources()
176 	hpriv->flags |= dpriv->pdata->hflags;  in ahci_dwc_get_resources()
177 	hpriv->plat_data = (void *)dpriv;  in ahci_dwc_get_resources()
184 	unsigned long port_map = hpriv->saved_port_map | hpriv->mask_port_map;  in ahci_dwc_check_cap()
185 	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;  in ahci_dwc_check_cap()
191 	param = readl(hpriv->mmio + AHCI_DWC_HOST_GPARAM2R);  in ahci_dwc_check_cap()
197 	if (!dev_mp && hpriv->saved_cap & HOST_CAP_MPS) {  in ahci_dwc_check_cap()
198 		dev_warn(&dpriv->pdev->dev, "MPS is unsupported\n");  in ahci_dwc_check_cap()
199 		hpriv->saved_cap &= ~HOST_CAP_MPS;  in ahci_dwc_check_cap()
204 		dev_warn(&dpriv->pdev->dev, "PMPn is limited up to %u ports\n",  in ahci_dwc_check_cap()
209 		if (!dev_mp && hpriv->saved_port_cap[i] & PORT_CMD_MPSP) {  in ahci_dwc_check_cap()
210 			dev_warn(&dpriv->pdev->dev, "MPS incapable port %d\n", i);  in ahci_dwc_check_cap()
211 			hpriv->saved_port_cap[i] &= ~PORT_CMD_MPSP;  in ahci_dwc_check_cap()
214 		if (!dev_cp && hpriv->saved_port_cap[i] & PORT_CMD_CPD) {  in ahci_dwc_check_cap()
215 			dev_warn(&dpriv->pdev->dev, "CPD incapable port %d\n", i);  in ahci_dwc_check_cap()
216 			hpriv->saved_port_cap[i] &= ~PORT_CMD_CPD;  in ahci_dwc_check_cap()
219 		if (!fbs_sup && hpriv->saved_port_cap[i] & PORT_CMD_FBSCP) {  in ahci_dwc_check_cap()
220 			dev_warn(&dpriv->pdev->dev, "FBS incapable port %d\n", i);  in ahci_dwc_check_cap()
221 			hpriv->saved_port_cap[i] &= ~PORT_CMD_FBSCP;  in ahci_dwc_check_cap()
228 	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;  in ahci_dwc_init_timer()
234 	cap = readl(hpriv->mmio + HOST_CAP);  in ahci_dwc_init_timer()
235 	cap2 = readl(hpriv->mmio + HOST_CAP2);  in ahci_dwc_init_timer()
248 	dpriv->timv = readl(hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);  in ahci_dwc_init_timer()
249 	dpriv->timv = FIELD_GET(AHCI_DWC_HOST_TIMV_MASK, dpriv->timv);  in ahci_dwc_init_timer()
251 	if (rate == dpriv->timv)  in ahci_dwc_init_timer()
254 	dev_info(&dpriv->pdev->dev, "Update CCC/DevSlp timer for Fapp %lu MHz\n",  in ahci_dwc_init_timer()
256 	dpriv->timv = FIELD_PREP(AHCI_DWC_HOST_TIMV_MASK, rate);  in ahci_dwc_init_timer()
257 	writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);  in ahci_dwc_init_timer()
262 	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;  in ahci_dwc_init_dmacr()
274 	for_each_child_of_node(dpriv->pdev->dev.of_node, child) {  in ahci_dwc_init_dmacr()
280 			return -EINVAL;  in ahci_dwc_init_dmacr()
286 		if (!of_property_read_u32(child, "snps,tx-ts-max", &ts)) {  in ahci_dwc_init_dmacr()
292 		if (!of_property_read_u32(child, "snps,rx-ts-max", &ts)) {  in ahci_dwc_init_dmacr()
299 		dpriv->dmacr[port] = dmacr;  in ahci_dwc_init_dmacr()
307 	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;  in ahci_dwc_init_host()
314 	if (dpriv->pdata->init) {  in ahci_dwc_init_host()
315 		rc = dpriv->pdata->init(hpriv);  in ahci_dwc_init_host()
331 	if (dpriv->pdata->clear)  in ahci_dwc_init_host()
332 		dpriv->pdata->clear(hpriv);  in ahci_dwc_init_host()
342 	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;  in ahci_dwc_reinit_host()
343 	unsigned long port_map = hpriv->port_map;  in ahci_dwc_reinit_host()
351 	if (dpriv->pdata->reinit) {  in ahci_dwc_reinit_host()
352 		rc = dpriv->pdata->reinit(hpriv);  in ahci_dwc_reinit_host()
357 	writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);  in ahci_dwc_reinit_host()
361 		writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR);  in ahci_dwc_reinit_host()
374 	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;  in ahci_dwc_clear_host()
376 	if (dpriv->pdata->clear)  in ahci_dwc_clear_host()
377 		dpriv->pdata->clear(hpriv);  in ahci_dwc_clear_host()
384 	struct ahci_host_priv *hpriv = host->private_data;  in ahci_dwc_stop_host()
434 	struct ahci_host_priv *hpriv = host->private_data;  in ahci_dwc_suspend()
449 	struct ahci_host_priv *hpriv = host->private_data;  in ahci_dwc_resume()
472 	{ .compatible = "snps,dwc-ahci", &ahci_dwc_plat },
473 	{ .compatible = "snps,spear-ahci", &ahci_dwc_plat },
474 	{ .compatible = "baikal,bt1-ahci", &ahci_bt1_plat },