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Searched +full:bmips +full:- +full:cbr +full:- +full:reg (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/arch/mips/bmips/ !
Dsetup.c22 #include <asm/bmips.h>
24 #include <asm/cpu-type.h>
27 #include <asm/smp-ops.h>
38 * CBR addr doesn't change and we can cache it.
39 * For broken SoC/Bootloader CBR addr might also be provided via DT
40 * with "brcm,bmips-cbr-reg" in the "cpus" node.
65 * load address to a non-conflicting region (e.g. via in bcm3384_viper_quirks()
71 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our in bcm3384_viper_quirks()
131 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
132 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
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/linux-6.12.1/Documentation/devicetree/bindings/mips/brcm/ !
Dsoc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 The experimental -viper variants are for running Linux on the 3384's
23 - brcm,bcm3368
24 - brcm,bcm3384
25 - brcm,bcm33843
26 - brcm,bcm3384-viper
27 - brcm,bcm33843-viper
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/linux-6.12.1/arch/mips/bcm63xx/ !
Dsetup.c15 #include <asm/bmips.h>
27 * CBR addr doesn't change and we can cache it.
28 * For broken SoC/Bootloader CBR addr might also be provided via DT
29 * with "brcm,bmips-cbr-reg" in the "cpus" node.
42 u32 reg; in bcm6348_a1_reboot() local
45 pr_info("soft-resetting all blocks ...\n"); in bcm6348_a1_reboot()
46 reg = bcm_perf_readl(PERF_SOFTRESET_REG); in bcm6348_a1_reboot()
47 reg &= ~SOFTRESET_6348_ALL; in bcm6348_a1_reboot()
48 bcm_perf_writel(reg, PERF_SOFTRESET_REG); in bcm6348_a1_reboot()
51 reg = bcm_perf_readl(PERF_SOFTRESET_REG); in bcm6348_a1_reboot()
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Dprom.c13 #include <asm/bmips.h>
14 #include <asm/smp-ops.h>
23 u32 reg, mask; in prom_init() local
25 /* Cache CBR addr before CPU/DMA setup */ in prom_init()
54 reg = bcm_perf_readl(PERF_CKCTL_REG); in prom_init()
55 reg &= ~mask; in prom_init()
56 bcm_perf_writel(reg, PERF_CKCTL_REG); in prom_init()
69 reg = bcm_readl(BCM_6328_OTP_BASE + in prom_init()
72 if (reg & OTP_6328_REG3_TP1_DISABLED) in prom_init()
/linux-6.12.1/arch/mips/bcm47xx/ !
Dsetup.c6 * Copyright (C) 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
40 #include <asm/bmips.h>
50 * CBR addr doesn't change and we can cache it.
51 * For broken SoC/Bootloader CBR addr might also be provided via DT
52 * with "brcm,bmips-cbr-reg" in the "cpus" node.
130 memcpy(&port, &mcore->serial_ports[0], sizeof(port)); in bcm47xx_register_ssb()
131 memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], in bcm47xx_register_ssb()
133 memcpy(&mcore->serial_ports[1], &port, sizeof(port)); in bcm47xx_register_ssb()
159 if (c->cputype == CPU_74K) { in plat_mem_setup()