mips/bmips/setup.c

22 #include <asm/bmips.h>
24 #include <asm/cpu-type.h>
27 #include <asm/smp-ops.h>
38  * CBR addr doesn't change and we can cache it.
39  * For broken SoC/Bootloader CBR addr might also be provided via DT
40  * with "brcm,bmips-cbr-reg" in the "cpus" node.
65 	 * load address to a non-conflicting region (e.g. via  in bcm3384_viper_quirks()
71 	 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our  in bcm3384_viper_quirks()
131 	{ "brcm,bcm3384-viper",		&bcm3384_viper_quirks		},
132 	{ "brcm,bcm33843-viper",	&bcm3384_viper_quirks		},
154 	/* Cache CBR addr before CPU/DMA setup */  in prom_init()
163 	return "Generic BMIPS kernel";  in get_system_type()
174 	if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)  in plat_time_init()
175 		panic("missing 'mips-hpt-frequency' property");  in plat_time_init()
204 	for (q = bmips_quirk_list; q->quirk_fn; q++) {  in plat_mem_setup()
206 					     q->compatible)) {  in plat_mem_setup()
207 			q->quirk_fn();  in plat_mem_setup()
227 	/* Check if DT provide a CBR address */  in device_tree_init()
228 	if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr))  in device_tree_init()
231 	/* Make sure CBR address is outside DRAM window */  in device_tree_init()
234 		WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n",  in device_tree_init()
240 	/* Since CBR is provided by DT, enable RAC flush */  in device_tree_init()