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Searched +full:bcm6345 +full:- +full:timer (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/timer/
Dbrcm,bcmbca-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/timer/brcm,bcmbca-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Broadband SoC timer
10 - Rafał Miłecki <rafal@milecki.pl>
15 - const: brcm,bcm6345-timer
19 It can be found in BCM6345, BCM6838 and BCM63268.
20 - const: brcm,bcm63138-timer
33 - reg
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/linux-6.12.1/arch/mips/boot/dts/brcm/
Dbcm63268.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm63268-clock.h"
4 #include "dt-bindings/reset/bcm63268-reset.h"
5 #include "dt-bindings/soc/bcm63268-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
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/linux-6.12.1/arch/arm64/boot/dts/broadcom/bcmbca/
Dbcm6858.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
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Dbcm4908.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/soc/bcm-pmb.h>
8 /dts-v1/;
11 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 stdout-path = "serial0:115200n8";
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Dbcm6856.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
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/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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Dbcm6846.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
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Dbcm63148.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "brcm,brahma-b15";
24 next-level-cache = <&L2_0>;
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/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Dbrcm,bcm7038-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/brcm,bcm7038-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM63xx and BCM7038 watchdog timer
10 - Florian Fainelli <f.fainelli@gmail.com>
11 - Justin Chen <justinpopo6@gmail.com>
12 - Rafał Miłecki <rafal@milecki.pl>
15 - $ref: watchdog.yaml#
20 - brcm,bcm6345-wdt
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/linux-6.12.1/drivers/watchdog/
Dbcm7038_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
41 * peripheral registers for CPU-native byte order. in bcm7038_wdt_write()
62 timeout = wdt->rate * wdog->timeout; in bcm7038_wdt_set_timeout_reg()
64 bcm7038_wdt_write(timeout, wdt->base + WDT_TIMEOUT_REG); in bcm7038_wdt_set_timeout_reg()
71 bcm7038_wdt_write(WDT_START_1, wdt->base + WDT_CMD_REG); in bcm7038_wdt_ping()
72 bcm7038_wdt_write(WDT_START_2, wdt->base + WDT_CMD_REG); in bcm7038_wdt_ping()
89 bcm7038_wdt_write(WDT_STOP_1, wdt->base + WDT_CMD_REG); in bcm7038_wdt_stop()
90 bcm7038_wdt_write(WDT_STOP_2, wdt->base + WDT_CMD_REG); in bcm7038_wdt_stop()
98 /* Can't modify timeout value if watchdog timer is running */ in bcm7038_wdt_set_timeout()
100 wdog->timeout = t; in bcm7038_wdt_set_timeout()
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/linux-6.12.1/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* BCM6345 clock bits are shifted by 16 on the left, because of the test
91 * control register which is 16-bits wide. That way we do not have any
92 * specific BCM6345 code for handling clocks, and writing 0 to the test
422 /* Timer irqstat register */
434 /* Timer control register */
996 /* Endpoint<->DMA mappings */
1003 /* Misc per-endpoint settings */
1267 #define SPI_6348_CMD 0x00 /* 16-bits register */
1276 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
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