Lines Matching +full:bcm6345 +full:- +full:timer

1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* BCM6345 clock bits are shifted by 16 on the left, because of the test
91  * control register which is 16-bits wide. That way we do not have any
92  * specific BCM6345 code for handling clocks, and writing 0 to the test
422 /* Timer irqstat register */
434 /* Timer control register */
996 /* Endpoint<->DMA mappings */
1003 /* Misc per-endpoint settings */
1267 #define SPI_6348_CMD			0x00	/* 16-bits register */
1276 #define SPI_6348_MSG_CTL		0x40	/* 8-bits register */
1284 #define SPI_6358_MSG_CTL		0x00	/* 16-bits register */
1290 #define SPI_6358_CMD			0x700	/* 16-bits register */