| /linux-6.12.1/drivers/spi/ |
| D | spi-xilinx.c | 116 static void xilinx_spi_tx(struct xilinx_spi *xspi) in xilinx_spi_tx() argument
120 if (!xspi->tx_ptr) { in xilinx_spi_tx()
121 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
125 switch (xspi->bytes_per_word) { in xilinx_spi_tx()
127 data = *(u8 *)(xspi->tx_ptr); in xilinx_spi_tx()
130 data = *(u16 *)(xspi->tx_ptr); in xilinx_spi_tx()
133 data = *(u32 *)(xspi->tx_ptr); in xilinx_spi_tx()
137 xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
138 xspi->tx_ptr += xspi->bytes_per_word; in xilinx_spi_tx()
141 static void xilinx_spi_rx(struct xilinx_spi *xspi) in xilinx_spi_rx() argument
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| D | spi-cadence.c | 134 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) in cdns_spi_read() argument
136 return readl_relaxed(xspi->regs + offset); in cdns_spi_read()
139 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) in cdns_spi_write() argument
141 writel_relaxed(val, xspi->regs + offset); in cdns_spi_write()
146 * @xspi: Pointer to the cdns_spi structure
156 static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target) in cdns_spi_init_hw() argument
163 if (xspi->is_decoded_cs) in cdns_spi_init_hw()
166 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); in cdns_spi_init_hw()
167 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL); in cdns_spi_init_hw()
170 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY) in cdns_spi_init_hw()
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| D | spi-xlp.c | 125 static void xlp_spi_sysctl_setup(struct xlp_spi_priv *xspi) in xlp_spi_sysctl_setup() argument
130 xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL, in xlp_spi_sysctl_setup()
132 xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL, XLP_SPI_SYS_PMEN); in xlp_spi_sysctl_setup()
137 struct xlp_spi_priv *xspi; in xlp_spi_setup() local
141 xspi = spi_controller_get_devdata(spi->controller); in xlp_spi_setup()
146 fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz); in xlp_spi_setup()
152 xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv); in xlp_spi_setup()
153 xlp_spi_reg_write(xspi, cs, XLP_SPI_FIFO_THRESH, XLP_SPI_TXRXTH); in xlp_spi_setup()
154 cfg = xlp_spi_reg_read(xspi, cs, XLP_SPI_CONFIG); in xlp_spi_setup()
175 xlp_spi_reg_write(xspi, cs, XLP_SPI_CONFIG, cfg); in xlp_spi_setup()
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| D | spi-xtensa-xtfpga.c | 43 static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi) in xtfpga_spi_wait_busy() argument
47 for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) && in xtfpga_spi_wait_busy()
56 struct xtfpga_spi *xspi = spi_controller_get_devdata(spi->controller); in xtfpga_spi_txrx_word() local
58 xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0)); in xtfpga_spi_txrx_word()
59 xspi->data_sz += bits; in xtfpga_spi_txrx_word()
60 if (xspi->data_sz >= 16) { in xtfpga_spi_txrx_word()
61 xtfpga_spi_write32(xspi, XTFPGA_SPI_DATA, in xtfpga_spi_txrx_word()
62 xspi->data >> (xspi->data_sz - 16)); in xtfpga_spi_txrx_word()
63 xspi->data_sz -= 16; in xtfpga_spi_txrx_word()
64 xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 1); in xtfpga_spi_txrx_word()
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| D | spi-cadence-xspi.c | 2 // Cadence XSPI flash controller driver
27 #define CDNS_XSPI_NAME "cadence-xspi"
31 * configure XSPI controller pin-strap settings
568 "Incorrect XSPI magic number: %x, expected: %x\n", in cdns_xspi_controller_init()
1273 .compatible = "cdns,xspi-nor",
1277 .compatible = "marvell,cn10-xspi-nor",
1294 MODULE_DESCRIPTION("Cadence XSPI Controller Driver");
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| D | spi-fsl-dspi.c | 240 * individually (in XSPI mode)
673 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One in dspi_pushr_cmd_write()
794 * Update CTAR here (code is common for XSPI and DMA modes). in dspi_setup_accel()
795 * We will update CTARE in the portion specific to XSPI, when we in dspi_setup_accel()
812 /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ in dspi_fifo_write()
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| D | Kconfig | 269 tristate "Cadence XSPI controller"
273 Enable support for the Cadence XSPI Flash controller.
275 Cadence XSPI is a specialized controller for connecting an SPI
277 device with a Cadence XSPI controller and want to access the
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| D | Makefile | 41 obj-$(CONFIG_SPI_CADENCE_XSPI) += spi-cadence-xspi.o
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| /linux-6.12.1/Documentation/devicetree/bindings/spi/ |
| D | cdns,xspi.yaml | 5 $id: http://devicetree.org/schemas/spi/cdns,xspi.yaml#
8 title: Cadence XSPI Controller
14 The XSPI controller allows SPI protocol communication in
21 - cdns,xspi-nor
22 - marvell,cn10-xspi-nor
55 - marvell,cn10-xspi-nor
78 xspi: spi@a0010000 {
81 compatible = "cdns,xspi-nor";
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| /linux-6.12.1/include/dt-bindings/memory/ |
| D | tegra234-mc.h | 289 /* XSPI writes */
339 /* XSPI client */
341 /* XSPI writes */
343 /* XSPI client */
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/renesas/ |
| D | renesas,r9a09g057-sys.yaml | 18 - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
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| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ |
| D | metrics.json | 339 "BriefDescription": "bytes of xspi read from ddr",
340 "MetricName": "imx95_ddr_read.xspi",
347 "BriefDescription": "bytes of xspi write to ddr",
348 "MetricName": "imx95_ddr_write.xspi",
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| /linux-6.12.1/drivers/mtd/spi-nor/ |
| D | spansion.c | 689 * On older versions of the flash the xSPI Profile 1.0 table has the in s28hx_t_post_sfdp_fixup()
700 * Since xSPI Page Program opcode is backward compatible with in s28hx_t_post_sfdp_fixup()
707 * The xSPI Profile 1.0 table advertises the number of additional in s28hx_t_post_sfdp_fixup()
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| D | sfdp.c | 24 #define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 table. */
1102 * Since xSPI Page Program opcode is backward compatible with in spi_nor_parse_4bait()
1150 * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
1224 * Page Program is "Required Command" in the xSPI Profile 1.0. Update in spi_nor_parse_profile1()
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| D | core.c | 2724 * Since xSPI Page Program opcode is backward compatible with in spi_nor_no_sfdp_init_params()
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