Home
last modified time | relevance | path

Searched full:tmu (Results 1 – 25 of 147) sorted by relevance

123456

/linux-6.12.1/Documentation/devicetree/bindings/timer/
Drenesas,tmu.yaml4 $id: http://devicetree.org/schemas/timer/renesas,tmu.yaml#
7 title: Renesas R-Mobile/R-Car Timer Unit (TMU)
14 The TMU is a 32-bit timer/counter with configurable clock inputs and
18 are independent. The TMU hardware supports up to three channels.
24 - renesas,tmu-r8a73a4 # R-Mobile APE6
25 - renesas,tmu-r8a7740 # R-Mobile A1
26 - renesas,tmu-r8a7742 # RZ/G1H
27 - renesas,tmu-r8a7743 # RZ/G1M
28 - renesas,tmu-r8a7744 # RZ/G1N
29 - renesas,tmu-r8a7745 # RZ/G1E
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/thermal/
Dsamsung,exynos-thermal.yaml7 title: Samsung Exynos SoC Thermal Management Unit (TMU)
13 For multi-instance tmu each instance should have an alias correctly numbered
19 - samsung,exynos3250-tmu
20 - samsung,exynos4412-tmu
21 - samsung,exynos4210-tmu
22 - samsung,exynos5250-tmu
23 - samsung,exynos5260-tmu
24 # For TMU channel 0, 1 on Exynos5420:
25 - samsung,exynos5420-tmu
26 # For TMU channels 2, 3 and 4 of Exynos5420:
[all …]
Dqoriq-thermal.yaml7 title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
19 The version of the device is determined by the TMU IP Block Revision
26 - fsl,qoriq-tmu
27 - fsl,imx8mq-tmu
35 fsl,tmu-range:
43 fsl,tmu-calibration:
59 boolean, if present, the TMU registers are little endian. If absent,
73 - fsl,tmu-range
74 - fsl,tmu-calibration
80 tmu@f0000 {
[all …]
Dimx8mm-thermal.yaml15 i.MX8MM has TMU IP to allow temperature measurement, there are
27 - fsl,imx8mm-tmu
28 - fsl,imx8mp-tmu
30 - const: fsl,imx8mn-tmu
31 - const: fsl,imx8mm-tmu
66 compatible = "fsl,imx8mm-tmu";
/linux-6.12.1/drivers/clocksource/
Dsh_tmu.c3 * SuperH Timer Support - TMU
39 struct sh_tmu_device *tmu; member
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
111 switch (ch->tmu->model) { in sh_tmu_write()
113 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
115 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
132 raw_spin_lock_irqsave(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
141 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
[all …]
/linux-6.12.1/drivers/thermal/
Dimx8mm_thermal.c21 #define TER 0x0 /* TMU enable */
23 #define TRITSR 0x20 /* TMU immediate temp */
24 /* TMU calibration data registers */
52 /* TMU OCOTP calibration data bitfields */
100 struct imx8mm_tmu *tmu = sensor->priv; in imx8mm_tmu_get_temp() local
103 val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK; in imx8mm_tmu_get_temp()
107 * ERR051272: TMU: Bit 31 of registers TMU_TSCR/TMU_TRITSR/TMU_TRATSR invalid in imx8mm_tmu_get_temp()
120 struct imx8mm_tmu *tmu = sensor->priv; in imx8mp_tmu_get_temp() local
124 val = readl_relaxed(tmu->base + TRITSR); in imx8mp_tmu_get_temp()
144 struct imx8mm_tmu *tmu = sensor->priv; in tmu_get_temp() local
[all …]
Dqoriq_thermal.c54 #define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring
96 * For TMU Rev1: in tmu_get_temp()
104 * For TMU Rev2: in tmu_get_temp()
192 len = of_property_count_u32_elems(np, "fsl,tmu-range"); in qoriq_tmu_calibration()
199 val = of_property_read_u32_array(np, "fsl,tmu-range", data->ttrcr, len); in qoriq_tmu_calibration()
209 calibration = of_get_property(np, "fsl,tmu-calibration", &len); in qoriq_tmu_calibration()
333 qoriq_tmu_init_device(data); /* TMU initialization */ in qoriq_tmu_probe()
335 ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */ in qoriq_tmu_probe()
381 { .compatible = "fsl,qoriq-tmu", },
382 { .compatible = "fsl,imx8mq-tmu", },
/linux-6.12.1/drivers/thunderbolt/
Dtmu.c3 * Thunderbolt Time Management Unit (TMU) support
73 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_set_tmu_mode_params()
81 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_set_tmu_mode_params()
86 sw->tmu.cap + TMU_RTR_CS_15, 1); in tb_switch_set_tmu_mode_params()
100 sw->tmu.cap + TMU_RTR_CS_15, 1); in tb_switch_set_tmu_mode_params()
108 sw->tmu.cap + TMU_RTR_CS_18, 1); in tb_switch_set_tmu_mode_params()
116 sw->tmu.cap + TMU_RTR_CS_18, 1); in tb_switch_set_tmu_mode_params()
128 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_tmu_ucap_is_supported()
141 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_read()
155 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_write()
[all …]
Dtb.h78 * enum tb_switch_tmu_mode - TMU mode
79 * @TB_SWITCH_TMU_MODE_OFF: TMU is off
85 * Ordering is based on TMU accuracy level (highest last).
96 * struct tb_switch_tmu - Structure holding router TMU configuration
97 * @cap: Offset to the TMU capability (%0 if not found)
99 * @mode: TMU mode related to the upstream router. Reflects the HW
101 * @mode_request: TMU mode requested to set. Related to upstream router.
120 * @tmu: The switch TMU configuration
134 * @cap_vsec_tmu: Offset to the TMU vendor specific capability (%0 if not found)
174 struct tb_switch_tmu tmu; member
[all …]
/linux-6.12.1/drivers/gpu/drm/v3d/
Dv3d_perfmon.c30 …{"QPU", "QPU-total-clk-cycles-waiting-TMU", "[QPU] Total clock cycles for all QPUs stalled waiting…
37 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
38 …{"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from mem…
62 {"TMU", "TMU-total-config-access", "[TMU] Total config accesses"},
65 {"L2T", "L2T-TMU-writes", "[L2T] TMU write accesses"},
66 {"TMU", "TMU-active-cycles", "[TMU] Active cycles"},
67 {"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"},
69 {"L2T", "L2T-TMU-reads", "[L2T] TMU read accesses"},
72 {"L2T", "L2T-TMU-config-reads", "[L2T] TMU CFG read accesses"},
76 {"L2T", "L2T-TMU-write-miss", "[L2T] TMU write misses"},
[all …]
/linux-6.12.1/Documentation/driver-api/thermal/
Dexynos_thermal.rst14 TMU controller Description:
46 TMU(Thermal Management Unit) in Exynos4/5 generates interrupt
64 TMU driver description:
74 TMU configuration data -----> TMU Driver <----> Exynos Core thermal wrapper
78 a) TMU configuration data:
79 This consist of TMU register offsets/bitfields
82 are used to configure the TMU.
83 b) TMU driver:
84 This component initialises the TMU controller and sets different
Dexynos_thermal_emulation.rst14 TMU's operation. User can set temperature manually with software code
15 and TMU will read current temperature from user value not from sensor's
/linux-6.12.1/drivers/platform/x86/intel/
Dbxtwc_tmu.c3 * Intel BXT Whiskey Cove PMIC TMU driver
7 * This driver adds TMU (Time Management Unit) support for Intel BXT platform.
8 * It enables the alarm wake-up functionality in the TMU unit of Whiskey Cove
38 /* Read TMU interrupt reg */ in bxt_wcove_tmu_irq_handler()
41 /* clear TMU irq */ in bxt_wcove_tmu_irq_handler()
84 /* Unmask TMU second level Wake & System alarm */ in bxt_wcove_tmu_probe()
97 /* Mask TMU interrupts */ in bxt_wcove_tmu_remove()
146 MODULE_DESCRIPTION("BXT Whiskey Cove TMU Driver");
DKconfig74 tristate "Intel Broxton Whiskey Cove TMU Driver"
79 Select this driver to use Intel Broxton Whiskey Cove PMIC TMU feature.
80 This driver enables the alarm wakeup functionality in the TMU unit of
/linux-6.12.1/drivers/thermal/samsung/
Dexynos_tmu.c3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
139 * struct exynos_tmu_data : A structure to hold the private data of the TMU
141 * @base: base address of the single instance of the TMU controller.
142 * @base_second: base address of the common registers of the TMU controller.
143 * @irq: irq number of the TMU controller.
148 * @sclk: pointer to the clock structure for accessing the tmu special clk.
161 * @enabled: current status of TMU device
167 * @tmu_initialize: SoC specific TMU initialization method
168 * @tmu_control: SoC specific TMU control method
169 * @tmu_read: SoC specific TMU temperature read method
[all …]
DKconfig7 If you say yes here you get support for the TMU (Thermal Management
9 the TMU, reports temperature and handles cooling action if defined.
10 This driver uses the Exynos core thermal APIs and TMU configuration
/linux-6.12.1/drivers/gpu/drm/vc4/
Dvc4_validate_shaders.c31 * (reading it as a texture, uniform data, or direct-addressed TMU
157 int tmu) in record_texture_sample() argument
170 &validation_state->tmu_setup[tmu], in record_texture_sample()
177 validation_state->tmu_setup[tmu].p_offset[i] = ~0; in record_texture_sample()
193 int tmu = waddr > QPU_W_TMU0_B; in check_tmu_write() local
195 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; in check_tmu_write()
203 DRM_DEBUG("direct TMU read used small immediate\n"); in check_tmu_write()
212 DRM_DEBUG("direct TMU load wasn't an add\n"); in check_tmu_write()
223 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
229 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/
Dclock-cpg.c60 clk_add_alias("fck", "sh-tmu-sh3.0", "peripheral_clk", NULL); in cpg_clk_init()
61 clk_add_alias("fck", "sh-tmu.0", "peripheral_clk", NULL); in cpg_clk_init()
62 clk_add_alias("fck", "sh-tmu.1", "peripheral_clk", NULL); in cpg_clk_init()
63 clk_add_alias("fck", "sh-tmu.2", "peripheral_clk", NULL); in cpg_clk_init()
/linux-6.12.1/arch/arm/boot/dts/samsung/
Dexynos5410.dtsi90 tmu_cpu0: tmu@10060000 {
91 compatible = "samsung,exynos5420-tmu";
99 tmu_cpu1: tmu@10064000 {
100 compatible = "samsung,exynos5420-tmu";
108 tmu_cpu2: tmu@10068000 {
109 compatible = "samsung,exynos5420-tmu";
117 tmu_cpu3: tmu@1006c000 {
118 compatible = "samsung,exynos5420-tmu";
/linux-6.12.1/arch/sh/kernel/cpu/sh4a/
Dclock-sh7786.c155 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
156 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
157 CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP010]),
158 CLKDEV_ICK_ID("fck", "sh-tmu.3", &mstp_clks[MSTP011]),
Dsetup-sh7770.c228 .name = "sh-tmu",
249 .name = "sh-tmu",
270 .name = "sh-tmu",
354 TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC, enumerator
407 INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
425 DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls208xa.dtsi86 thermal-sensors = <&tmu 1>;
100 thermal-sensors = <&tmu 2>;
114 thermal-sensors = <&tmu 3>;
128 thermal-sensors = <&tmu 4>;
157 thermal-sensors = <&tmu 5>;
186 thermal-sensors = <&tmu 6>;
215 thermal-sensors = <&tmu 7>;
314 tmu: tmu@1f80000 { label
315 compatible = "fsl,qoriq-tmu";
318 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
[all …]
Dfsl-ls1046a.dtsi128 thermal-sensors = <&tmu 0>;
148 thermal-sensors = <&tmu 1>;
168 thermal-sensors = <&tmu 2>;
188 thermal-sensors = <&tmu 3>;
219 thermal-sensors = <&tmu 4>;
439 tmu: tmu@1f00000 { label
440 compatible = "fsl,qoriq-tmu";
443 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
444 fsl,tmu-calibration =
Dfsl-ls1043a.dtsi160 thermal-sensors = <&tmu 0>;
180 thermal-sensors = <&tmu 1>;
200 thermal-sensors = <&tmu 2>;
220 thermal-sensors = <&tmu 3>;
251 thermal-sensors = <&tmu 4>;
443 tmu: tmu@1f00000 { label
444 compatible = "fsl,qoriq-tmu";
447 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
448 fsl,tmu-calibration =
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dt1023si-post.dtsi365 tmu: tmu@f0000 { label
366 compatible = "fsl,qoriq-tmu";
369 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
370 fsl,tmu-calibration =
418 thermal-sensors = <&tmu 0>;

123456