drm/v3d/v3d_perfmon.c

30 …{"QPU", "QPU-total-clk-cycles-waiting-TMU", "[QPU] Total clock cycles for all QPUs stalled waiting…
37 	{"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
38 …{"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from mem…
62 	{"TMU", "TMU-total-config-access", "[TMU] Total config accesses"},
65 	{"L2T", "L2T-TMU-writes", "[L2T] TMU write accesses"},
66 	{"TMU", "TMU-active-cycles", "[TMU] Active cycles"},
67 	{"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"},
69 	{"L2T", "L2T-TMU-reads", "[L2T] TMU read accesses"},
72 	{"L2T", "L2T-TMU-config-reads", "[L2T] TMU CFG read accesses"},
76 	{"L2T", "L2T-TMU-write-miss", "[L2T] TMU write misses"},
77 	{"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"},
80 	{"L2T", "L2T-TMU-config-read-miss", "[L2T] TMU CFG read misses"},
98 	{"TMU", "TMU-MRU-hits", "[TMU] Total MRU hits"},
125 	{"TMU", "TMU-active-cycles", "[TMU] Active cycles"},
126 	{"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"},
127 	{"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
128 	{"TMU", "TMU-cache-x4-active-cycles", "[TMU] Cache active cycles for x4 access"},
129 	{"TMU", "TMU-cache-x4-stalled-cycles", "[TMU] Cache stalled cycles for x4 access"},
130 	{"TMU", "TMU-total-text-quads-x4-access", "[TMU] Total texture cache x4 access"},
147 	{"L2T", "L2T-TMU-read-hits", "[L2T] TMU read hits"},
148 	{"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"},
190 	{"QPU", "QPU-stalls-TMU", "[QPU] Stalled qcycles waiting for TMU"},