| /linux-6.12.1/drivers/soundwire/ |
| D | intel.c | 75 void __iomem *s = sdw->link_res->shim; in intel_reg_show()
204 * shim ops
209 void __iomem *shim = sdw->link_res->shim; in intel_shim_glue_to_master_ip() local
214 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); in intel_shim_glue_to_master_ip()
217 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); in intel_shim_glue_to_master_ip()
221 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); in intel_shim_glue_to_master_ip()
225 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); in intel_shim_glue_to_master_ip()
230 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); in intel_shim_glue_to_master_ip()
240 void __iomem *shim = sdw->link_res->shim; in intel_shim_master_ip_to_glue() local
244 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); in intel_shim_master_ip_to_glue()
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| D | intel.h | 16 * @shim: Audio shim pointer
17 * @shim_vs: Audio vendor-specific shim pointer
20 * @ops: Shim callback ops
22 * @shim_lock: mutex to handle access to shared SHIM registers
23 * @shim_mask: global pointer to check SHIM register initialization
36 void __iomem *shim; member
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| D | intel_ace2x.c | 23 * shim vendor-specific (vs) ops
336 /* the SHIM will be configured in the callback functions */ in intel_hw_params()
399 * need to reinitialize the SHIM/ALH/Cadence IP. in intel_prepare()
401 * but in those cases we cannot touch ALH/SHIM in intel_prepare()
412 /* the SHIM will be configured in the callback functions */ in intel_prepare()
507 * In the case of xruns, the DMAs and SHIM registers cannot be touched, in intel_trigger()
508 * but for resume operations the DMAs and SHIM registers need to be initialized. in intel_trigger()
549 void __iomem *shim = sdw->link_res->shim; in intel_pdi_init() local
553 pcm_cap = intel_readw(shim, SDW_SHIM2_PCMSCAP); in intel_pdi_init()
566 void __iomem *shim = sdw->link_res->shim; in intel_pdi_get_ch_cap() local
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_hdcp.c | 182 const struct intel_hdcp_shim *shim, u8 *bksv) in intel_hdcp_read_valid_bksv() argument
189 ret = shim->read_bksv(dig_port, bksv); in intel_hdcp_read_valid_bksv()
207 const struct intel_hdcp_shim *shim = connector->hdcp.shim; in intel_hdcp_get_capability() local
216 if (!shim) in intel_hdcp_get_capability()
219 if (shim->hdcp_get_capability) { in intel_hdcp_get_capability()
220 shim->hdcp_get_capability(dig_port, &capable); in intel_hdcp_get_capability()
222 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) in intel_hdcp_get_capability()
269 hdcp->shim->hdcp_2_2_get_capability(connector, &capable); in intel_hdcp2_get_capability()
280 if (!hdcp->shim->get_remote_hdcp_capability) in intel_hdcp_get_remote_capability()
283 hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, in intel_hdcp_get_remote_capability()
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| /linux-6.12.1/Documentation/devicetree/bindings/media/ |
| D | ti,j721e-csi2rx-shim.yaml | 4 $id: http://devicetree.org/schemas/media/ti,j721e-csi2rx-shim.yaml#
7 title: TI J721E CSI2RX Shim
10 The TI J721E CSI2RX Shim is a wrapper around Cadence CSI2RX bridge that
12 Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the
20 const: ti,j721e-csi2rx-shim
64 compatible = "ti,j721e-csi2rx-shim";
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| /linux-6.12.1/Documentation/sound/hd-audio/ |
| D | intel-multi-link.rst | 93 - power management moved from SHIM to LCTL.SPA bits
94 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
96 - move of SHIM and Cadence registers to different offsets, with no
146 … | SDIID14 | | | SoundWire SHIM | |
151 … +---------------+ | | SoundWire SHIM | |
156 | SYNCGO | | | SoundWire SHIM |
161 +---------------+ | | SoundWire SHIM |
185 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
225 | | DMIC SHIM |
230 +---------------+ | | DMIC SHIM |
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| /linux-6.12.1/sound/soc/intel/atom/sst/ |
| D | sst_loader.c | 59 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
64 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
65 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
70 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
72 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
88 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in sst_start_mrfld()
92 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in sst_start_mrfld()
94 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in sst_start_mrfld()
99 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in sst_start_mrfld()
101 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in sst_start_mrfld()
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| D | sst_acpi.c | 176 /* Get Shim addr */ in sst_platform_get_resources()
180 dev_err(ctx->dev, "Invalid SHIM base from IFWI\n"); in sst_platform_get_resources()
207 dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add); in sst_platform_get_resources()
208 ctx->shim = devm_ioremap(ctx->dev, ctx->shim_phy_add, in sst_platform_get_resources()
210 if (!ctx->shim) { in sst_platform_get_resources()
211 dev_err(ctx->dev, "unable to map SHIM\n"); in sst_platform_get_resources()
302 * DDR, SHIM, MBOX, IRAM, DRAM, CFG in sst_acpi_probe()
304 * lpe8086_res_info.acpi_lpe_res_index points to the SHIM. in sst_acpi_probe()
311 dev_err(dev, "Invalid SHIM base\n"); in sst_acpi_probe()
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| D | sst_ipc.c | 126 header.full = sst_shim_read64(sst_drv_ctx->shim, SST_IPCX); in sst_post_message_mrfld()
137 header.full = sst_shim_read64(sst_drv_ctx->shim, SST_IPCX); in sst_post_message_mrfld()
169 sst_shim_write64(sst_drv_ctx->shim, SST_IPCX, msg->mrfld_header.full); in sst_post_message_mrfld()
186 imr.full = sst_shim_read64(sst_drv_ctx->shim, SST_IMRX); in intel_sst_clear_intr_mrfld()
187 isr.full = sst_shim_read64(sst_drv_ctx->shim, SST_ISRX); in intel_sst_clear_intr_mrfld()
191 sst_shim_write64(sst_drv_ctx->shim, SST_ISRX, isr.full); in intel_sst_clear_intr_mrfld()
194 clear_ipc.full = sst_shim_read64(sst_drv_ctx->shim, SST_IPCD); in intel_sst_clear_intr_mrfld()
199 sst_shim_write64(sst_drv_ctx->shim, SST_IPCD, clear_ipc.full); in intel_sst_clear_intr_mrfld()
202 sst_shim_write64(sst_drv_ctx->shim, SST_IMRX, imr.full); in intel_sst_clear_intr_mrfld()
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| D | sst_pci.c | 62 /* SHIM */ in sst_platform_get_resources()
64 ctx->shim = pcim_iomap(pci, 1, pci_resource_len(pci, 1)); in sst_platform_get_resources()
65 if (!ctx->shim) { in sst_platform_get_resources()
69 dev_dbg(ctx->dev, "SST Shim Ptr %p\n", ctx->shim); in sst_platform_get_resources()
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| D | sst.h | 34 /* SST Shim register map */
74 /* SST shim registers to structure mapping */
326 * @shim : SST shim pointer
331 * @shim_phy_add : SST shim phy addr
340 * @ipc_spin_lock : spin lock to handle audio shim access and ipc queue
360 void __iomem *shim; member
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| /linux-6.12.1/sound/soc/intel/common/ |
| D | sst-dsp-priv.h | 22 /* Shim IO */
43 void __iomem *shim; member
57 * Generic SST Shim Interface.
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| D | sst-dsp.c | 53 sst->ops->write(sst->addr.shim, offset, value); in sst_dsp_shim_write()
64 val = sst->ops->read(sst->addr.shim, offset); in sst_dsp_shim_read()
73 sst->ops->write(sst->addr.shim, offset, value); in sst_dsp_shim_write_unlocked()
79 return sst->ops->read(sst->addr.shim, offset); in sst_dsp_shim_read_unlocked()
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| /linux-6.12.1/sound/soc/codecs/ |
| D | max9877.c | 6 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
170 MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>");
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| D | max9877.h | 6 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
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| /linux-6.12.1/drivers/gpu/drm/exynos/ |
| D | exynos_drm_plane.h | 4 * Authors: Joonyoung Shim <jy0922.shim@samsung.com>
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| D | exynos_drm_fbdev.h | 7 * Joonyoung Shim <jy0922.shim@samsung.com>
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| D | exynos_drm_fb.h | 6 * Joonyoung Shim <jy0922.shim@samsung.com>
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| D | exynos_drm_crtc.h | 7 * Joonyoung Shim <jy0922.shim@samsung.com>
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| /linux-6.12.1/arch/arm/mach-s3c/ |
| D | usb-phy.h | 4 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
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| D | keypad.h | 6 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
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| /linux-6.12.1/drivers/pinctrl/intel/ |
| D | Kconfig.tng | 21 Intel Merrifield Family-Level Interface Shim (FLIS) driver provides
29 Intel Moorefield Family-Level Interface Shim (FLIS) driver provides
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| /linux-6.12.1/drivers/hid/intel-ish-hid/ |
| D | ishtp-fw-loader.c | 23 * ISH Shim firmware loader reserves 4 Kb buffer in SRAM. The buffer is
24 * used to temporarily hold the data transferred from host to Shim
34 * @LOADER_CMD_XFER_QUERY: Query the Shim firmware loader for
71 * instead manage the DMA directly in kernel driver and Shim firmware
106 * between Host driver and ISH Shim firmware loader.
461 * ish_query_loader_prop() - Query ISH Shim firmware loader
466 * This function queries the ISH Shim firmware loader for capabilities.
525 "ISH firmware size %zu is greater than Shim firmware loader max supported %d\n", in ish_query_loader_prop()
535 "Shim firmware loader buffer size %d should be multiple of cacheline\n", in ish_query_loader_prop()
651 * (2) Max DMA buffer size supported by Shim firmware, in ish_fw_xfer_direct_dma()
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| /linux-6.12.1/include/linux/input/ |
| D | samsung-keypad.h | 6 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
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| /linux-6.12.1/drivers/media/platform/ti/j721e-csi2rx/ |
| D | j721e-csi2rx.c | 3 * TI CSI2RX Shim Wrapper Driver
97 void __iomem *shim; member
495 writel(reg, csi->shim + SHIM_CNTL); in ti_csi2rx_setup_shim()
533 writel(reg, csi->shim + SHIM_DMACNTX); in ti_csi2rx_setup_shim()
537 writel(reg, csi->shim + SHIM_PSI_CFG0); in ti_csi2rx_setup_shim()
850 writel(0, csi->shim + SHIM_CNTL); in ti_csi2rx_start_streaming()
851 writel(0, csi->shim + SHIM_DMACNTX); in ti_csi2rx_start_streaming()
864 writel(0, csi->shim + SHIM_CNTL); in ti_csi2rx_stop_streaming()
865 writel(0, csi->shim + SHIM_DMACNTX); in ti_csi2rx_stop_streaming()
1101 csi->shim = devm_platform_ioremap_resource(pdev, 0); in ti_csi2rx_probe()
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