| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-am654-serdes.yaml | 4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
7 title: TI AM654 SERDES
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
19 - ti,phy-am654-serdes
26 - const: serdes
41 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
43 ti,serdes-clk:
44 description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
52 description: Phandle to the SYSCON entry required for configuring SERDES lane function.
56 - description: Clock output names for SERDES 0
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| D | mscc,vsc7514-serdes.yaml | 4 $id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
7 title: Microsemi Ocelot SerDes muxing
15 space for setting up the SerDes to switch port muxing.
17 A SerDes X can be "muxed" to work with switch port Y or Z for example.
18 One specific SerDes can also be used as a PCIe interface.
20 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
22 There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
35 - mscc,vsc7514-serdes
40 The first number defines the input port to use for a given SerDes macro.
42 dt-bindings/phy/phy-ocelot-serdes.h
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| D | microchip,sparx5-serdes.yaml | 4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
7 title: Microchip Sparx5 Serdes controller
13 The Sparx5 SERDES interfaces share the same basic functionality, but
16 The following list lists the SERDES features:
31 The SERDES6G is a high-speed SERDES interface, which can operate at
41 The SERDES10G is a high-speed SERDES interface, which can operate at
54 The SERDES25G is a high-speed SERDES interface, which can operate at
67 pattern: "^serdes@[0-9a-f]+$"
70 const: microchip,sparx5-serdes
78 - The main serdes input port
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| D | microchip,lan966x-serdes.yaml | 4 $id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#
7 title: Microchip Lan966x Serdes controller
16 interfaces. The Serdes controller will allow to configure these interfaces
23 interface SerDes 2.
27 pattern: "^serdes@[0-9a-f]+$"
30 const: microchip,lan966x-serdes
42 dt-bindings/phy/phy-lan966x-serdes.
53 serdes: serdes@e2004010 {
54 compatible = "microchip,lan966x-serdes";
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| D | ti,phy-j721e-wiz.yaml | 8 title: TI J721E WIZ (SERDES Wrapper)
61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
118 the SERDES.
148 provided by the SERDES.
166 "^serdes@[0-9a-f]+$":
169 WIZ node should have '1' subnode for the SERDES. It could be either
170 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
173 Torrent SERDES should follow the bindings specified in
248 serdes@5000000 {
250 reg-names = "serdes";
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| D | renesas,r8a779f0-ether-serdes.yaml | 4 $id: http://devicetree.org/schemas/phy/renesas,r8a779f0-ether-serdes.yaml#
7 title: Renesas Ethernet SERDES
14 const: renesas,r8a779f0-ether-serdes
29 description: Port number of SERDES.
48 compatible = "renesas,r8a779f0-ether-serdes";
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| /linux-6.12.1/arch/arm64/boot/dts/microchip/ |
| D | sparx5_pcb135_board.dtsi | 367 phys = <&serdes 13>;
374 phys = <&serdes 13>;
381 phys = <&serdes 13>;
388 phys = <&serdes 13>;
395 phys = <&serdes 14>;
402 phys = <&serdes 14>;
409 phys = <&serdes 14>;
416 phys = <&serdes 14>;
423 phys = <&serdes 15>;
430 phys = <&serdes 15>;
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| /linux-6.12.1/arch/arm64/boot/dts/amd/ |
| D | amd-seattle-xgbe-b.dtsi | 40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
48 amd,serdes-blwc = <1>, <1>, <0>;
49 amd,serdes-cdr-rate = <2>, <2>, <7>;
50 amd,serdes-pq-skew = <10>, <10>, <18>;
51 amd,serdes-tx-amp = <0>, <0>, <0>;
52 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
53 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
66 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | amd-xgbe.txt | 8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
43 - amd,serdes-blwc: Baseline wandering correction enablement
46 - amd,serdes-cdr-rate: CDR rate speed selection
47 - amd,serdes-pq-skew: PQ (data sampling) skew
48 - amd,serdes-tx-amp: TX amplitude boost
49 - amd,serdes-dfe-tap-config: DFE taps available to run
50 - amd,serdes-dfe-tap-enable: DFE taps to enable
70 amd,serdes-blwc = <1>, <1>, <0>;
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| D | hisilicon-hns-dsaf.txt | 17 The second region is SerDes base register and size(optional, only used when
18 serdes-syscon in port node does not exist). It is recommended using
19 serdes-syscon rather than this address.
40 - serdes-syscon: is syscon handle for SerDes register.
81 serdes-syscon = <&serdes>;
87 serdes-syscon = <&serdes>;
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| D | microchip,sparx5-switch.yaml | 97 phandle of a Ethernet SerDes PHY. This defines which SerDes
157 phys = <&serdes 13>;
166 phys = <&serdes 29>;
175 phys = <&serdes 30>;
184 phys = <&serdes 31>;
193 phys = <&serdes 32>;
203 phys = <&serdes 0>;
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| /linux-6.12.1/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-pcie-msm8996.c | 144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
173 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
185 void __iomem *serdes; member
284 void __iomem *serdes = qphy->serdes; in qmp_pcie_msm8996_serdes_init() local
291 qmp_configure(qmp->dev, serdes, serdes_tbl, serdes_tbl_num); in qmp_pcie_msm8996_serdes_init()
293 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); in qmp_pcie_msm8996_serdes_init()
294 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], in qmp_pcie_msm8996_serdes_init()
297 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; in qmp_pcie_msm8996_serdes_init()
313 void __iomem *serdes = qphy->serdes; in qmp_pcie_msm8996_com_init() local
344 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], in qmp_pcie_msm8996_com_init()
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| D | phy-qcom-qmp-ufs.c | 953 u16 serdes; member
962 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
963 const struct qmp_phy_init_tbl *serdes; member
983 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
1006 void __iomem *serdes; member
1054 .serdes = 0,
1063 .serdes = 0,
1078 .serdes = msm8996_ufsphy_serdes,
1101 .serdes = sm8350_ufsphy_serdes,
1111 .serdes = sm8350_ufsphy_hs_b_serdes,
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| /linux-6.12.1/arch/arm/boot/dts/microchip/ |
| D | lan966x-pcb8290.dts | 11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
120 phys = <&serdes 0 SERDES6G(1)>;
128 phys = <&serdes 1 SERDES6G(1)>;
136 phys = <&serdes 2 SERDES6G(1)>;
144 phys = <&serdes 3 SERDES6G(1)>;
152 phys = <&serdes 4 SERDES6G(2)>;
160 phys = <&serdes 5 SERDES6G(2)>;
168 phys = <&serdes 6 SERDES6G(2)>;
176 phys = <&serdes 7 SERDES6G(2)>;
180 &serdes {
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| D | lan966x-kontron-kswitch-d10-mmt.dtsi | 8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
155 phys = <&serdes 0 CU(0)>;
162 phys = <&serdes 1 CU(1)>;
169 phys = <&serdes 4 SERDES6G(2)>;
176 phys = <&serdes 5 SERDES6G(2)>;
183 phys = <&serdes 6 SERDES6G(2)>;
190 phys = <&serdes 7 SERDES6G(2)>;
196 &serdes {
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| /linux-6.12.1/drivers/phy/mscc/ |
| D | phy-ocelot-serdes.c | 3 * SerDes PHY driver for Microsemi Ocelot
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
60 static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode) in serdes_init_s6g() argument
89 ret = serdes_update_mcb_s6g(regmap, serdes); in serdes_init_s6g()
146 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
222 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
230 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
244 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
292 static int serdes_init_s1g(struct regmap *regmap, u8 serdes) in serdes_init_s1g() argument
296 ret = serdes_update_mcb_s1g(regmap, serdes); in serdes_init_s1g()
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| /linux-6.12.1/drivers/net/ethernet/sfc/falcon/ |
| D | enum.h | 17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
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| /linux-6.12.1/drivers/net/ethernet/sfc/siena/ |
| D | enum.h | 17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
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| /linux-6.12.1/drivers/net/ethernet/sfc/ |
| D | enum.h | 17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
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| /linux-6.12.1/drivers/net/dsa/mv88e6xxx/ |
| D | pcs-639x.c | 3 * Marvell 88E6352 family SERDES PCS support
17 #include "serdes.h"
78 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port); in mv88e639x_pcs_alloc()
218 * After chip reset, SERDES reconfiguration or SERDES core in mv88e6390_erratum_3_14()
219 * Software Reset, the SERDES lanes may not be properly aligned in mv88e6390_erratum_3_14()
269 "can't read Serdes PHY %s: %pe\n", in mv88e639x_sgmii_pcs_get_state()
278 "can't read Serdes PHY %s: %pe\n", in mv88e639x_sgmii_pcs_get_state()
287 "can't read Serdes PHY %s: %pe\n", in mv88e639x_sgmii_pcs_get_state()
364 "can't access Serdes PHY %s: %pe\n", in mv88e639x_sgmii_pcs_link_up()
409 "can't read Serdes PHY %s: %pe\n", in mv88e639x_xg_pcs_get_state()
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| /linux-6.12.1/drivers/phy/microchip/ |
| D | Kconfig | 7 tristate "Microchip Sparx5 SerDes PHY driver"
13 Enable this for support of the 10G/25G SerDes on Microchip Sparx5.
16 tristate "SerDes PHY driver for Microchip LAN966X"
21 Enable this for supporting SerDes muxing with Microchip LAN966X
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| /linux-6.12.1/drivers/phy/marvell/ |
| D | Kconfig | 36 shared serdes PHYs on Marvell Armada 3700. Its serdes lanes can be
55 shared serdes PHYs on Marvell Armada 38x. Its serdes lanes can be
66 shared serdes PHYs on Marvell Armada 7k/8k (in the CP110). Its serdes
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| /linux-6.12.1/drivers/net/ethernet/intel/ice/ |
| D | ice_ptp_consts.h | 88 .serdes = 0x6666, /* 51.2 */
94 .serdes = 0xffffc59a, /* -29.2 */
107 .serdes = 0x28f6, /* 20.48 */
113 .serdes = 0xffffe8a4, /* -11.68 */
125 .serdes = 0x234c, /* 17.6484848 */
132 .serdes = 0xffffeb27, /* -10.42424 */
165 .serdes = 0xe1e, /* 7.0593939 */
173 .serdes = 0xfffff7a9, /* -4.1697 */
194 .serdes = 0x234c, /* 17.6484848 */
201 .serdes = 0xffffeb27, /* -10.42424 */
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/ti/ |
| D | ti,am654-serdes-ctrl.yaml | 4 $id: http://devicetree.org/schemas/soc/ti/ti,am654-serdes-ctrl.yaml#
7 title: Texas Instruments AM654 Serdes Control Syscon
15 - const: ti,am654-serdes-ctrl
35 compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";
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| /linux-6.12.1/drivers/phy/ti/ |
| D | Kconfig | 25 tristate "TI AM654 SERDES support"
33 This option enables support for TI AM654 SerDes PHY used for
37 tristate "TI J721E WIZ (SERDES Wrapper) support"
47 SoC. WIZ is a serdes wrapper used to configure some of the input
48 signals to the SERDES (Sierra/Torrent). This driver configures
|