Lines Matching full:serdes

3  * Marvell 88E6352 family SERDES PCS support
17 #include "serdes.h"
78 		 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port);  in mv88e639x_pcs_alloc()
218 	 * After chip reset, SERDES reconfiguration or SERDES core  in mv88e6390_erratum_3_14()
219 	 * Software Reset, the SERDES lanes may not be properly aligned  in mv88e6390_erratum_3_14()
269 			"can't read Serdes PHY %s: %pe\n",  in mv88e639x_sgmii_pcs_get_state()
278 			"can't read Serdes PHY %s: %pe\n",  in mv88e639x_sgmii_pcs_get_state()
287 			"can't read Serdes PHY %s: %pe\n",  in mv88e639x_sgmii_pcs_get_state()
364 			"can't access Serdes PHY %s: %pe\n",  in mv88e639x_sgmii_pcs_link_up()
409 			"can't read Serdes PHY %s: %pe\n",  in mv88e639x_xg_pcs_get_state()
612  * Cannot clear PwrDn bit on SERDES if device is configured CPU_MGD mode or
614  * Workaround: Set SERDES register 4.F002 bit 5=0 and bit 15=1.
616  * It seems that after this workaround the SERDES is automatically powered up
643  * When a SERDES port is operating in 1000BASE-X or SGMII mode link may not
644  * come up after hardware reset or software reset of SERDES core. Workaround
645  * is to write SERDES register 4.F074.14=1 for only those modes and 0 in all
671  * SERDES operating in 10G mode. These registers only apply to 10G operation
704  * writing value 0x58 to register 1e.8000. (This must be done while SerDes
710  * SerDes at 1.25 GHz and does not change the 1e.8000 register, leaving SerDes
712  * To avoid this, change PCS mode back to 2500base-x when disabling SerDes from