| /linux-6.12.1/drivers/i2c/busses/ |
| D | i2c-pasemi-core.c | 5 * SMBus host driver for PA Semi PWRficient
45 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) in reg_write() argument
47 dev_dbg(smbus->dev, "smbus write reg %x val %08x\n", reg, val); in reg_write()
48 iowrite32(val, smbus->ioaddr + reg); in reg_write()
51 static inline int reg_read(struct pasemi_smbus *smbus, int reg) in reg_read() argument
54 ret = ioread32(smbus->ioaddr + reg); in reg_read()
55 dev_dbg(smbus->dev, "smbus read reg %x val %08x\n", reg, ret); in reg_read()
59 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg)) argument
60 #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO) argument
62 static void pasemi_reset(struct pasemi_smbus *smbus) in pasemi_reset() argument
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| D | i2c-amd8111.c | 3 * SMBus 2.0 driver for AMD-8111 IO-Hub.
21 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
68 static int amd_ec_wait_write(struct amd_smbus *smbus) in amd_ec_wait_write() argument
72 while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout) in amd_ec_wait_write()
76 dev_warn(&smbus->dev->dev, in amd_ec_wait_write()
84 static int amd_ec_wait_read(struct amd_smbus *smbus) in amd_ec_wait_read() argument
88 while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout) in amd_ec_wait_read()
92 dev_warn(&smbus->dev->dev, in amd_ec_wait_read()
100 static int amd_ec_read(struct amd_smbus *smbus, unsigned char address, in amd_ec_read() argument
105 status = amd_ec_wait_write(smbus); in amd_ec_read()
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| D | i2c-nforce2.c | 3 SMBus driver for nVidia nForce2 MCP
9 SMBus 2.0 driver for AMD-8111 IO-Hub
35 /* Note: we assume there can only be one nForce2, with two SMBus interfaces */
51 MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");
64 * nVidia nForce2 SMBus control register definitions
72 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
74 #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
75 #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
76 #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
77 #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
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| D | i2c-pasemi-platform.c | 5 * PA Semi PWRficient SMBus host driver for Apple SoCs
19 struct pasemi_smbus smbus; member
32 data->smbus.clk_div = DIV_ROUND_UP(clk_rate, 16 * frequency); in pasemi_platform_i2c_calc_clk_div()
33 if (data->smbus.clk_div < 4) in pasemi_platform_i2c_calc_clk_div()
34 return dev_err_probe(data->smbus.dev, -EINVAL, in pasemi_platform_i2c_calc_clk_div()
37 if (data->smbus.clk_div > 0xff) in pasemi_platform_i2c_calc_clk_div()
38 return dev_err_probe(data->smbus.dev, -EINVAL, in pasemi_platform_i2c_calc_clk_div()
49 struct pasemi_smbus *smbus; in pasemi_platform_i2c_probe() local
59 smbus = &data->smbus; in pasemi_platform_i2c_probe()
60 smbus->dev = dev; in pasemi_platform_i2c_probe()
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| D | i2c-pasemi-pci.c | 5 * SMBus host driver for PA Semi PWRficient
28 struct pasemi_smbus *smbus; in pasemi_smb_pci_probe() local
36 smbus = devm_kzalloc(&dev->dev, sizeof(*smbus), GFP_KERNEL); in pasemi_smb_pci_probe()
37 if (!smbus) in pasemi_smb_pci_probe()
40 smbus->dev = &dev->dev; in pasemi_smb_pci_probe()
43 smbus->clk_div = CLK_100K_DIV; in pasemi_smb_pci_probe()
49 smbus->hw_rev = PASEMI_HW_REV_PCI; in pasemi_smb_pci_probe()
55 smbus->ioaddr = pcim_iomap(dev, 0, 0); in pasemi_smb_pci_probe()
56 if (!smbus->ioaddr) in pasemi_smb_pci_probe()
59 smbus->adapter.class = I2C_CLASS_HWMON; in pasemi_smb_pci_probe()
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| D | i2c-piix4.c | 18 SMBus interfaces.
32 #include <linux/i2c-smbus.h>
39 /* PIIX4 SMBus address offsets */
188 "SMBus base address memory region 0x%x already in use.\n", in piix4_sb800_region_request()
198 dev_err(dev, "SMBus base address mapping failed.\n"); in piix4_sb800_region_request()
210 "SMBus base address index region 0x%x already in use.\n", in piix4_sb800_region_request()
235 * w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on in piix4_sb800_use_mmio()
253 /* On some motherboards, it was reported that accessing the SMBus in piix4_setup()
257 "Accessing the SMBus on this system is unsafe!\n"); in piix4_setup()
261 /* Don't access SMBus on IBM systems which get corrupted eeproms */ in piix4_setup()
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| D | i2c-viapro.c | 30 Note: we assume there can only be one device, with one SMBus interface.
50 /* SMBus address offsets */
62 /* SMBus data in configuration space can be found in two places,
84 MODULE_PARM_DESC(force, "Forcibly enable the SMBus. DANGEROUS!");
91 "Forcibly enable the SMBus at the given address. "
136 /* Make sure the SMBus host is ready to start transmitting */ in vt596_transaction()
138 dev_dbg(&vt596_adapter.dev, "SMBus busy (0x%02x). " in vt596_transaction()
143 dev_err(&vt596_adapter.dev, "SMBus reset failed! " in vt596_transaction()
158 /* If the SMBus is still busy, we give up */ in vt596_transaction()
161 dev_err(&vt596_adapter.dev, "SMBus timeout!\n"); in vt596_transaction()
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| D | i2c-sis96x.c | 17 We assume there can only be one SiS96x with one SMBus interface.
33 /* SiS96x SMBus registers */
54 /* SiS96x SMBus constants */
76 /* Execute a SMBus transaction.
85 dev_dbg(&sis96x_adapter.dev, "SMBus transaction %d\n", size); in sis96x_transaction()
87 /* Make sure the SMBus host is ready to start transmitting */ in sis96x_transaction()
90 dev_dbg(&sis96x_adapter.dev, "SMBus busy (0x%02x). " in sis96x_transaction()
121 /* If the SMBus is still busy, we give up */ in sis96x_transaction()
123 dev_dbg(&sis96x_adapter.dev, "SMBus Timeout! (0x%02x)\n", temp); in sis96x_transaction()
261 dev_err(&dev->dev, "SiS96x SMBus base address " in sis96x_probe()
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| D | i2c-isch.c | 3 i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus
15 Note: we assume there can only be one device, with one SMBus interface.
27 /* SCH SMBus address offsets */
69 /* Make sure the SMBus host is ready to start transmitting */ in sch_transaction()
78 dev_dbg(&sch_adapter.dev, "SMBus error (%02x). " in sch_transaction()
85 "SMBus is not ready: (%02x)\n", temp); in sch_transaction()
98 /* If the SMBus is still busy, we give up */ in sch_transaction()
100 dev_err(&sch_adapter.dev, "SMBus Timeout!\n"); in sch_transaction()
104 dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be " in sch_transaction()
143 /* Make sure the SMBus host is not busy */ in sch_access()
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| D | i2c-amd756.c | 22 Note: we assume there can only be one device, with one SMBus interface.
35 /* AMD756 SMBus address offsets */
76 SMBUS event = I/O 28-29 bit 11
107 /* Make sure the SMBus host is ready to start transmitting */ in amd756_transaction()
109 dev_dbg(&adap->dev, "SMBus busy (%04x). Waiting...\n", temp); in amd756_transaction()
115 /* If the SMBus is still busy, we give up */ in amd756_transaction()
132 /* If the SMBus is still busy, we give up */ in amd756_transaction()
140 dev_dbg(&adap->dev, "SMBus Protocol error (no response)!\n"); in amd756_transaction()
145 dev_warn(&adap->dev, "SMBus collision!\n"); in amd756_transaction()
150 dev_dbg(&adap->dev, "SMBus protocol timeout!\n"); in amd756_transaction()
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| D | Kconfig | 9 comment "PC SMBus host controller drivers"
59 support for the first (SMBus 1.0) I2C interface of the AMD 8111 and
66 tristate "SMBus multiplexing on the Tyan S4882"
69 Enabling this option will add specific SMBus support for the Tyan
70 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
83 second (SMBus 2.0) AMD 8111 mainboard I2C interface.
172 Optional support for multiplexed SMBUS on certain systems with
176 tristate "Intel SCH SMBus 1.0"
180 Say Y here if you want to use SMBus controller on the Intel SCH
187 tristate "Intel iSMT SMBus Controller"
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| /linux-6.12.1/Documentation/i2c/ |
| D | smbus-protocol.rst | 2 The SMBus Protocol
5 The following is a summary of the SMBus protocol. It applies to
10 Some adapters understand only the SMBus (System Management Bus) protocol,
12 only the same subset, which makes it possible to put them on an SMBus.
14 If you write a driver for some I2C device, please try to use the SMBus
17 SMBus adapters and I2C adapters (the SMBus command set is automatically
19 handled at all on most pure SMBus adapters).
21 Below is a list of SMBus protocol operations, and the functions executing
22 them. Note that the names used in the SMBus protocol specifications usually
24 single data byte, the functions using SMBus protocol operation names execute
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| D | functionality.rst | 2 I2C/SMBus Functionality
8 Because not every I2C or SMBus adapter implements everything in the
22 I2C_FUNC_I2C Plain i2c-level commands (Pure SMBus
29 I2C_FUNC_SMBUS_QUICK Handles the SMBus write_quick command
30 I2C_FUNC_SMBUS_READ_BYTE Handles the SMBus read_byte command
31 I2C_FUNC_SMBUS_WRITE_BYTE Handles the SMBus write_byte command
32 I2C_FUNC_SMBUS_READ_BYTE_DATA Handles the SMBus read_byte_data command
33 I2C_FUNC_SMBUS_WRITE_BYTE_DATA Handles the SMBus write_byte_data command
34 I2C_FUNC_SMBUS_READ_WORD_DATA Handles the SMBus read_word_data command
35 I2C_FUNC_SMBUS_WRITE_WORD_DATA Handles the SMBus write_byte_data command
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| D | fault-codes.rst | 2 I2C/SMBUS Fault Codes
6 codes in the I2C/SMBus stack.
26 I2C and SMBus fault codes
56 Returned by SMBus logic when an invalid Packet Error Code byte
59 fault is only reported on read transactions; the SMBus slave
65 Returned by SMBus adapters when the bus was busy for longer
67 SMBus adapter) needs some fault recovery (such as resetting),
106 doesn't support SMBus block transfers is asked to execute
119 or SMBus (or chip-specific) protocol specifications. One
120 case is when the length of an SMBus block data response
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| D | i2c-stub.rst | 8 This module is a very simple fake I2C/SMBus driver. It implements six
9 types of SMBus commands: write quick, (r/w) byte, (r/w) byte data, (r/w)
10 word data, (r/w) I2C block data, and (r/w) SMBus block data.
13 driver, which will then only react to SMBus commands to these addresses.
25 SMBus block command support is disabled by default, and must be enabled
29 SMBus block commands must be written to configure an SMBus command for
30 SMBus block operations. Writes can be partial. Block read commands always
47 The SMBus addresses to emulate chips at.
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| D | summary.rst | 2 Introduction to I2C and SMBus
18 SMBus (System Management Bus) is based on the I2C protocol, and is mostly
20 SMBus, but some SMBus protocols add semantics beyond what is required to
21 achieve I2C branding. Modern PC mainboards rely on SMBus. The most common
22 devices connected through SMBus are RAM modules configured using I2C EEPROMs,
25 Because the SMBus is mostly a subset of the generalized I2C bus, we can
27 meet both SMBus and I2C electrical constraints; and others which can't
28 implement all the common SMBus protocol semantics or messages.
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| D | dev-interface.rst | 28 #include <i2c/smbus.h>
58 Well, you are all set up now. You can now use SMBus commands or plain
59 I2C to communicate with your device. SMBus commands are preferred if
66 /* Using SMBus commands */
92 Note that only a subset of the I2C and SMBus protocols can be achieved by
118 Selects SMBus PEC (packet error checking) generation and verification
120 Used only for SMBus transactions. This request only has an effect if the
151 You can do SMBus level transactions (see documentation file smbus-protocol.rst
195 device you want to access) and I2C_PEC (enable or disable SMBus error
201 performs an SMBus transaction using i2c-core-smbus.c:i2c_smbus_xfer().
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| /linux-6.12.1/Documentation/i2c/busses/ |
| D | i2c-i801.rst | 55 On Intel Patsburg and later chipsets, both the normal host SMBus controller
73 0x01 disable SMBus PEC
77 0x20 disable SMBus Host Notify
99 The SMBus controller is function 3 in device 1f. Class 0c05 is SMBus Serial
103 SMBus controller.
118 SMBus 2.0 Support
121 The 82801DB (ICH4) and later chips support several SMBus 2.0 features.
130 Hidden ICH SMBus
134 SMBus device at 00:1f.3 in lspci, and you can't figure out any way in the
140 SMBus was hidden on purpose because it'll be driven by ACPI. If the
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| D | i2c-piix4.rst | 45 SMBus - you can not access it on I2C levels. The good news is that it
46 natively understands SMBus commands and you do not have to worry about
47 timing problems. The bad news is that non-SMBus devices connected to it can
58 find such an entry, you have a PIIX4 SMBus controller.
60 On some computers (most notably, some Dells), the SMBus is disabled by
67 'force' does, but it will also set a new base I/O port address. The SMBus
74 The PIIX/PIIX3 does not implement an SMBus or I2C bus, so you can't use
78 identical to the PIIX4 in I2C/SMBus support.
81 PIIX4-compatible SMBus controllers. If your BIOS initializes the
83 an "Auxiliary SMBus Host Controller".
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| D | i2c-amd8111.rst | 6 * AMD-8111 SMBus 2.0 PCI interface
20 00:07.2 SMBus: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0 (rev 02)
21 Subsystem: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0
32 SMBus 2.0 Support
41 Note that for the 8111, there are two SMBus adapters. The SMBus 2.0 adapter
42 is supported by this driver, and the SMBus 1.0 adapter is supported by the
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| /linux-6.12.1/drivers/i2c/ |
| D | i2c-core-smbus.c | 3 * Linux I2C core SMBus and SMBus emulation code
5 * This file contains the SMBus functions which are always included in the I2C
6 * core because they can be emulated via I2C. SMBus specific extensions
7 * (e.g. smbalert) are handled in a separate i2c-smbus module.
9 * All SMBus-related things are written by Frodo Looijaard <frodol@dds.nl>
10 * SMBus 2.0 support by Mark Studebaker <mdsxyz123@yahoo.com> and
16 #include <linux/i2c-smbus.h>
23 #include <trace/events/smbus.h>
26 /* The SMBus parts */
59 /* Assume a 7-bit address, which is reasonable for SMBus */
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| D | Kconfig | 14 many micro controller applications and developed by Philips. SMBus,
19 Both I2C and SMBus are supported here. You will need this for
90 tristate "SMBus-specific protocols" if !I2C_HELPER_AUTO
92 Say Y here if you want support for SMBus extensions to the I2C
94 the SMBus Alert protocol and the SMBus Host Notify protocol.
97 will be called i2c-smbus.
103 tristate "I2C/SMBus Test Stub"
106 This module may be useful to developers of SMBus client drivers,
134 multi-master, SMBus Host Notify, etc. Please read
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| /linux-6.12.1/Documentation/driver-api/ |
| D | i2c.rst | 1 I\ :sup:`2`\ C and SMBus Subsystem
29 The System Management Bus (SMBus) is a sibling protocol. Most SMBus
31 for SMBus, and it standardizes particular protocol messages and idioms.
32 Controllers that support I2C can also support most SMBus operations, but
33 SMBus controllers don't support all the protocol options that an I2C
34 controller will. There are functions to perform various SMBus protocol
35 operations, either using I2C primitives or by issuing SMBus commands to
47 .. kernel-doc:: drivers/i2c/i2c-core-smbus.c
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| /linux-6.12.1/Documentation/translations/it_IT/i2c/ |
| D | summary.rst | 2 Introduzione a I2C e SMBus
22 SMBus (Bus per la gestione del sistema) si basa sul protocollo I2C ed è
24 I2C funzioneranno su SMBus, ma alcuni protocolli SMBus aggiungono semantica
26 SMBus. I più comuni dispositivi collegati tramite SMBus sono moduli RAM
30 Poiché SMBus è principalmente un sottoinsieme del bus I2C,
32 soddisfano i vincoli elettrici sia di SMBus che di I2C; e altri che non possono
33 implementare tutta la semantica o messaggi comuni del protocollo SMBus.
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| /linux-6.12.1/drivers/misc/eeprom/ |
| D | idt_89hpesx.c | 11 * NOTE of the IDT 89HPESx SMBus-slave interface driver
13 * IDT PCIe-switches. IDT provides a simple SMBus interface to perform IO-
15 * SMBus of switches. Using that interface this the driver creates a simple
20 * Additionally IDT 89HPESx SMBus interface has an ability to write/read
55 #define IDT_89HPESX_DESC "IDT 89HPESx SMBus-slave interface driver"
80 * @smb_write: SMBus write method
81 * @smb_read: SMBus read method
82 * @smb_mtx: SMBus mutex
112 * @ccode: SMBus command code
149 * SMBus command code macros
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