| /linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | pllgt215.c | 42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
51 fN = tmp % info->refclk; in gt215_pll_calc()
54 if (fN >= info->refclk / 2) in gt215_pll_calc()
57 if (fN < info->refclk / 2) in gt215_pll_calc()
59 fN = tmp - (N * info->refclk); in gt215_pll_calc()
67 err = abs(freq - (info->refclk * N / M / *P)); in gt215_pll_calc()
75 *pfN = ((fN << 13) + info->refclk / 2) / info->refclk; in gt215_pll_calc()
86 return info->refclk * *pN / *pM / *P; in gt215_pll_calc()
|
| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 1270 u16 refclk; member
1276 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1277 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1278 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1279 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1280 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1285 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1286 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1287 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1292 { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
[all …]
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| D | intel_dpll.c | 237 /* LVDS 100mhz refclk limits. */
316 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
322 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
334 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params() argument
340 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
347 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params() argument
353 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
360 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params() argument
366 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22); in chv_calc_dpll_params()
430 int refclk = i9xx_pll_refclk(crtc_state); in i9xx_crtc_clock_get() local
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/pinctrl/ |
| D | mediatek,mt7620-pinctrl.yaml | 39 pa, pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf,
40 refclk, rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite,
41 wdt refclk, wdt rst, wled]
70 spi refclk, uartf, uartlite, wdt, wled]
138 const: pcie refclk
183 const: refclk
228 const: spi refclk
232 enum: [spi refclk]
255 const: wdt refclk
|
| /linux-6.12.1/drivers/phy/ti/ |
| D | phy-dm816x-usb.c | 46 struct clk *refclk; member
76 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
77 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
123 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_suspend()
134 error = clk_enable(phy->refclk); in dm816x_usb_phy_runtime_resume()
151 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_resume()
218 phy->refclk = devm_clk_get(phy->dev, "refclk"); in dm816x_usb_phy_probe()
219 if (IS_ERR(phy->refclk)) in dm816x_usb_phy_probe()
220 return PTR_ERR(phy->refclk); in dm816x_usb_phy_probe()
221 error = clk_prepare(phy->refclk); in dm816x_usb_phy_probe()
[all …]
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| D | phy-ti-pipe3.c | 172 struct clk *refclk; member
608 phy->refclk = devm_clk_get(dev, "refclk"); in ti_pipe3_get_clk()
609 if (IS_ERR(phy->refclk)) { in ti_pipe3_get_clk()
610 dev_err(dev, "unable to get refclk\n"); in ti_pipe3_get_clk()
611 /* older DTBs have missing refclk in SATA PHY in ti_pipe3_get_clk()
615 return PTR_ERR(phy->refclk); in ti_pipe3_get_clk()
817 * Prevent auto-disable of refclk for SATA PHY due to Errata i783 in ti_pipe3_probe()
820 if (!IS_ERR(phy->refclk)) { in ti_pipe3_probe()
821 clk_prepare_enable(phy->refclk); in ti_pipe3_probe()
843 clk_disable_unprepare(phy->refclk); in ti_pipe3_remove()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/usb/ |
| D | smsc,usb3503.yaml | 64 Clock used for driving REFCLK signal. If not provided the driver assumes
70 const: refclk
72 refclk-frequency:
75 Frequency of the REFCLK signal as defined by REF_SEL pins. If not
76 provided, driver will not set rate of the REFCLK signal and assume that a
122 clock-names = "refclk";
141 clock-names = "refclk";
156 refclk-frequency = <19200000>;
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| D | octeon-usb.txt | 24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
54 cavium,refclk-type = "crystal";
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| D | dcn32_dccg.c | 161 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
170 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
179 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
188 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
268 * Assume refclk is sourced from xtalin in dccg32_get_dccg_ref_freq()
284 /* always program refclk as DTBCLK. No use-case expected to require DPREFCLK as refclk */ in dccg32_set_dpstreamclk()
292 (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
296 (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
300 (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
304 (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
|
| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | fsl,imx8-pcie-phy.yaml | 43 fsl,refclk-pad-mode:
45 Specifies the mode of the refclk pad used. It can be UNUSED(PHY
47 is provided externally via the refclk pad) or OUTPUT(PHY refclock
48 is derived from SoC internal source and provided on the refclk pad).
79 - fsl,refclk-pad-mode
99 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
| D | ti,phy-j721e-wiz.yaml | 74 refclk-dig:
113 "^pll[0|1]-refclk$":
216 pll0-refclk {
223 pll1-refclk {
230 cmn-refclk-dig-div {
240 refclk-dig {
|
| /linux-6.12.1/drivers/phy/xilinx/ |
| D | phy-zynqmp.c | 105 /* Refclk selection parameters */
206 * @refclk: reference clock index
215 unsigned int refclk; member
407 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; in xpsgtr_configure_pll()
414 if (gtr_phy->refclk == gtr_phy->lane) in xpsgtr_configure_pll()
419 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); in xpsgtr_configure_pll()
639 if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk])) in xpsgtr_phy_init()
691 clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]); in xpsgtr_phy_exit()
795 unsigned int refclk; in xpsgtr_xlate() local
825 refclk = args->args[3]; in xpsgtr_xlate()
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/arc/ |
| D | emac_rockchip.c | 32 struct clk *refclk; member
147 priv->refclk = devm_clk_get(dev, "macref"); in emac_rockchip_probe()
148 if (IS_ERR(priv->refclk)) { in emac_rockchip_probe()
150 PTR_ERR(priv->refclk)); in emac_rockchip_probe()
151 err = PTR_ERR(priv->refclk); in emac_rockchip_probe()
155 err = clk_prepare_enable(priv->refclk); in emac_rockchip_probe()
195 err = clk_set_rate(priv->refclk, 50000000); in emac_rockchip_probe()
241 clk_disable_unprepare(priv->refclk); in emac_rockchip_probe()
254 clk_disable_unprepare(priv->refclk); in emac_rockchip_remove()
|
| /linux-6.12.1/drivers/gpu/drm/loongson/ |
| D | lsdc_pixpll.h | 14 * refclk: reference frequency, 100 MHz from external oscillator
19 * refclk +-----------+ +------------------+ +---------+ outclk
29 * outclk = refclk / div_ref * loopc / div_out;
38 * 1) 20 MHz <= refclk / div_ref <= 40Mhz
39 * 2) 1.2 GHz <= refclk /div_out * loopc <= 3.2 Ghz
|
| /linux-6.12.1/arch/mips/bcm63xx/ |
| D | clk.c | 423 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
424 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
440 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
441 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
454 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
468 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
482 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
497 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
498 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
516 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/gma500/ |
| D | gma_display.h | 44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
83 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
88 struct drm_crtc *crtc, int target, int refclk,
|
| D | oaktrail_crtc.c | 41 int refclk, struct gma_clock_t *best_clock);
45 int refclk, struct gma_clock_t *best_clock);
84 int refclk) in mrst_limit() argument
113 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
114 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
116 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
128 int refclk, struct gma_clock_t *best_clock) in mrst_sdvo_find_best_pll() argument
153 actual_freq = (refclk * clock.m) / in mrst_sdvo_find_best_pll()
181 * Returns a set of divisors for the desired target clock with the given refclk,
186 int refclk, struct gma_clock_t *best_clock) in mrst_lvds_find_best_pll() argument
[all …]
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| D | cdv_intel_display.c | 25 int refclk, struct gma_clock_t *best_clock);
365 int refclk) in cdv_intel_limit() argument
373 if (refclk == 96000) in cdv_intel_limit()
379 if (refclk == 27000) in cdv_intel_limit()
384 if (refclk == 27000) in cdv_intel_limit()
393 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
397 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
403 int refclk, in cdv_intel_find_dp_pll() argument
411 switch (refclk) { in cdv_intel_find_dp_pll()
448 gma_crtc->clock_funcs->clock(refclk, &clock); in cdv_intel_find_dp_pll()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| D | dcn314_dccg.c | 162 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
171 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
180 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
189 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
264 DPSTREAMCLK0_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
269 DPSTREAMCLK1_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
274 DPSTREAMCLK2_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
279 DPSTREAMCLK3_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
292 /* Set HPO stream encoder to use refclk to avoid case where PHY is in dccg314_init()
305 dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst, in dccg314_init()
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| /linux-6.12.1/drivers/pci/controller/cadence/ |
| D | pci-j721e.c | 56 struct clk *refclk; member
248 /* Clear PAD IO disable bits to enable refclk output */ in j721e_enable_acspcie_refclk()
252 dev_err(dev, "failed to enable ACSPCIE refclk: %d\n", ret); in j721e_enable_acspcie_refclk()
298 /* Enable ACSPCIE refclk output if the optional property exists */ in j721e_pcie_ctrl_init()
572 pcie->refclk = clk; in j721e_pcie_probe()
578 * should be deasserted after minimum of 100us once REFCLK is in j721e_pcie_probe()
579 * stable. The REFCLK to the connector in RC mode is selected in j721e_pcie_probe()
589 clk_disable_unprepare(pcie->refclk); in j721e_pcie_probe()
626 clk_disable_unprepare(pcie->refclk); in j721e_pcie_remove()
638 clk_disable_unprepare(pcie->refclk); in j721e_pcie_suspend_noirq()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
30 refclk-frequency = <24000000>;
32 refclk-type = "crystal";
|
| /linux-6.12.1/drivers/net/ethernet/ti/ |
| D | cpts.c | 559 err = clk_enable(cpts->refclk); in cpts_register()
580 clk_disable(cpts->refclk); in cpts_register()
600 clk_disable(cpts->refclk); in cpts_unregister()
609 freq = clk_get_rate(cpts->refclk); in cpts_calc_mult_shift()
660 refclk_np = of_get_child_by_name(node, "cpts-refclk-mux"); in cpts_of_mux_clk_setup()
662 /* refclk selection supported not for all SoCs */ in cpts_of_mux_clk_setup()
767 cpts->refclk = devm_get_clk_from_child(dev, node, "cpts"); in cpts_create()
768 if (IS_ERR(cpts->refclk)) in cpts_create()
770 cpts->refclk = devm_clk_get(dev, "cpts"); in cpts_create()
772 if (IS_ERR(cpts->refclk)) { in cpts_create()
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/synaptics/ |
| D | berlin2cd.dtsi | 51 refclk: oscillator { label
389 clocks = <&refclk>;
390 clock-names = "refclk";
446 clocks = <&refclk>;
453 clocks = <&refclk>;
461 clocks = <&refclk>;
486 clocks = <&refclk>;
497 clocks = <&refclk>;
507 clocks = <&refclk>;
532 clocks = <&refclk>;
[all …]
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| /linux-6.12.1/drivers/clk/berlin/ |
| D | bg2.c | 90 REFCLK, VIDEO_EXT0, enumerator
103 [REFCLK] = "refclk",
516 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2_clock_setup()
518 clk_names[REFCLK] = __clk_get_name(clk); in berlin2_clock_setup()
530 clk_names[SYSPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
535 clk_names[MEMPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
540 clk_names[CPUPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
549 clk_names[REFCLK], avpll_flags, 0); in berlin2_clock_setup()
562 clk_names[REFCLK], BERLIN2_AVPLL_BIT_QUIRK | in berlin2_clock_setup()
577 parent_names[1] = clk_names[REFCLK]; in berlin2_clock_setup()
[all …]
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| /linux-6.12.1/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt7620.c | 60 FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
63 static struct mtmips_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
79 FUNC("wdt refclk", 0, 17, 1),
83 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
101 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
|