237 /* LVDS 100mhz refclk limits. */
316 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)  in pnv_calc_dpll_params()  argument
322 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in pnv_calc_dpll_params()
334 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)  in i9xx_calc_dpll_params()  argument
340 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);  in i9xx_calc_dpll_params()
347 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)  in vlv_calc_dpll_params()  argument
353 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in vlv_calc_dpll_params()
360 int chv_calc_dpll_params(int refclk, struct dpll *clock)  in chv_calc_dpll_params()  argument
366 		DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);  in chv_calc_dpll_params()
430 	int refclk = i9xx_pll_refclk(crtc_state);  in i9xx_crtc_clock_get()  local
471 			port_clock = pnv_calc_dpll_params(refclk, &clock);  in i9xx_crtc_clock_get()
473 			port_clock = i9xx_calc_dpll_params(refclk, &clock);  in i9xx_crtc_clock_get()
502 		port_clock = i9xx_calc_dpll_params(refclk, &clock);  in i9xx_crtc_clock_get()
520 	int refclk = 100000;  in vlv_crtc_clock_get()  local
538 	crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);  in vlv_crtc_clock_get()
550 	int refclk = 100000;  in chv_crtc_clock_get()  local
572 	crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);  in chv_crtc_clock_get()
576  * Returns whether the given set of divisors are valid for a given refclk with
641  * refclk, or FALSE.
651 		    int target, int refclk,  in i9xx_find_best_dpll()  argument
675 					i9xx_calc_dpll_params(refclk, &clock);  in i9xx_find_best_dpll()
699  * refclk, or FALSE.
709 		   int target, int refclk,  in pnv_find_best_dpll()  argument
731 					pnv_calc_dpll_params(refclk, &clock);  in pnv_find_best_dpll()
755  * refclk, or FALSE.
765 		   int target, int refclk,  in g4x_find_best_dpll()  argument
792 					i9xx_calc_dpll_params(refclk, &clock);  in g4x_find_best_dpll()
854  * refclk, or FALSE.
859 		   int target, int refclk,  in vlv_find_best_dpll()  argument
868 	int max_n = min(limit->n.max, refclk / 19200);  in vlv_find_best_dpll()
884 								     refclk * clock.m1);  in vlv_find_best_dpll()
886 					vlv_calc_dpll_params(refclk, &clock);  in vlv_find_best_dpll()
912  * refclk, or FALSE.
917 		   int target, int refclk,  in chv_find_best_dpll()  argument
933 	 * set to 2.  If requires to support 200Mhz refclk, we need to  in chv_find_best_dpll()
948 						   refclk * clock.m1);  in chv_find_best_dpll()
955 			chv_calc_dpll_params(refclk, &clock);  in chv_find_best_dpll()
977 	int refclk = 100000;  in bxt_find_best_dpll()  local
980 				  crtc_state->port_clock, refclk,  in bxt_find_best_dpll()
1360 	int refclk = 120000;  in ilk_crtc_compute_clock()  local
1372 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in ilk_crtc_compute_clock()
1376 			if (refclk == 100000)  in ilk_crtc_compute_clock()
1381 			if (refclk == 100000)  in ilk_crtc_compute_clock()
1392 				refclk, NULL, &crtc_state->dpll))  in ilk_crtc_compute_clock()
1395 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in ilk_crtc_compute_clock()
1481 	int refclk = 100000;  in chv_crtc_compute_clock()  local
1485 				refclk, NULL, &crtc_state->dpll))  in chv_crtc_compute_clock()
1488 	chv_calc_dpll_params(refclk, &crtc_state->dpll);  in chv_crtc_compute_clock()
1508 	int refclk = 100000;  in vlv_crtc_compute_clock()  local
1512 				refclk, NULL, &crtc_state->dpll))  in vlv_crtc_compute_clock()
1515 	vlv_calc_dpll_params(refclk, &crtc_state->dpll);  in vlv_crtc_compute_clock()
1536 	int refclk = 96000;  in g4x_crtc_compute_clock()  local
1540 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in g4x_crtc_compute_clock()
1543 				    refclk);  in g4x_crtc_compute_clock()
1562 				refclk, NULL, &crtc_state->dpll))  in g4x_crtc_compute_clock()
1565 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in g4x_crtc_compute_clock()
1585 	int refclk = 96000;  in pnv_crtc_compute_clock()  local
1589 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in pnv_crtc_compute_clock()
1592 				    refclk);  in pnv_crtc_compute_clock()
1602 				refclk, NULL, &crtc_state->dpll))  in pnv_crtc_compute_clock()
1605 	pnv_calc_dpll_params(refclk, &crtc_state->dpll);  in pnv_crtc_compute_clock()
1623 	int refclk = 96000;  in i9xx_crtc_compute_clock()  local
1627 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in i9xx_crtc_compute_clock()
1630 				    refclk);  in i9xx_crtc_compute_clock()
1640 				 refclk, NULL, &crtc_state->dpll))  in i9xx_crtc_compute_clock()
1643 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in i9xx_crtc_compute_clock()
1663 	int refclk = 48000;  in i8xx_crtc_compute_clock()  local
1667 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in i8xx_crtc_compute_clock()
1670 				    refclk);  in i8xx_crtc_compute_clock()
1682 				 refclk, NULL, &crtc_state->dpll))  in i8xx_crtc_compute_clock()
1685 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in i8xx_crtc_compute_clock()
2019 	/* Enable Refclk */  in vlv_enable_pll()
2057 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()
2166 	/* Enable Refclk and SSC */  in chv_enable_pll()